define CACHE_LINE_SIZE in arch_*.h

[urcu.git] / tests / test_rwlock.c

diff --git a/tests/test_rwlock.c b/tests/test_rwlock.c
index d3f072ce14350e2c54b6cdb07c13e42f50ed1e87..923ecad946b050e4c1535efba941aa8d5cdf1b1b 100644 (file)
--- a/tests/test_rwlock.c
+++ b/tests/test_rwlock.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384