move everything out of trunk

[lttv.git] / markers-test / test-mark-speed.c

diff --git a/markers-test/test-mark-speed.c b/markers-test/test-mark-speed.c
index f41acb575b3cd1c395345e54e5e167c2f503d92a..015ce4997f7c7cab9b52c014bdaa225dcc23dd3e 100644 (file)
--- a/markers-test/test-mark-speed.c
+++ b/markers-test/test-mark-speed.c
@@ -10,6 +10,28 @@
 #include <asm/ptrace.h>
 #include <asm/system.h>
 
+static void pmc_flush_cache(void)
+{
+    register int i;
+    /* write back and invalidate cache (a serializing instruction) */
+
+    __asm__ __volatile__ ( "wbinvd" : : : "memory" );
+
+    /* The wbinvd instruction does not wait for the external caches
+     * to be flushed, but only requests that it be done.  The loop
+     * is to be sure that enough time has elapsed, but the compiler
+     * might simplify or even remove it.  The loop bound is for a
+     * 512 KB L2 cache.  On a Pentium Pro/II/III, the loop uses
+     * 2 cycles per iteration.
+     *
+     * Does wbinvd also cause the TLB to be flushed?
+     * A comment in mtrr.c suggests that it does.
+     */
+    for (i = 0; i < 512*1024; i++) {
+       cpu_relax();
+    }
+}
+
 static void noinline test2(const struct marker *mdata,
         void *call_private, ...)
 {
@@ -17,6 +39,12 @@ static void noinline test2(const struct marker *mdata,
        printk("blah\n");
 }
 
+#ifdef CACHEFLUSH
+#define myclflush(a) clflush(a)
+#else
+#define myclflush(a)
+#endif                                                                 \
+
 /*
  * Generic marker flavor always available.
  * Note : the empty asm volatile with read constraint is used here instead of a
@@ -42,6 +70,7 @@ static void noinline test2(const struct marker *mdata,
                                        (&__mark_##name, call_private,  \
                                        ## args);               \
                } else {                                                \
+                       myclflush(&_imv_read(__mark_##name.state));     \
                        if (unlikely(_imv_read(__mark_##name.state)))   \
                                test2                   \
                                        (&__mark_##name, call_private,  \
@@ -52,15 +81,13 @@ static void noinline test2(const struct marker *mdata,
        //asm volatile ("");
 struct proc_dir_entry *pentry = NULL;
 
-int temp __cacheline_aligned = 10;
-int temp2 __cacheline_aligned = 10;
-
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-#ifdef CACHEFLUSH
-       wbinvd();
-#endif
-       temp = (temp + 60) << 10;
+       volatile int temp[5];
+       temp[2] = (temp[0] + 60) << 10;
+       temp[3] = (temp[2] + 60) << 10;
+       temp[4] = (temp[3] + 60) << 10;
+       temp[0] = (temp[4] + 60) << 10;
        //asm volatile ("");
        barrier();
        __my_trace_mark(1, kernel_debug_test, NULL, "%d %d %ld %ld", 2, current->pid, arg, arg2);
@@ -75,6 +102,10 @@ static int my_open(struct inode *inode, struct file *file)
        unsigned long flags;
 
        local_irq_save(flags);
+#ifdef CACHEFLUSH
+       //pmc_flush_cache();    /* initial write back, without cycle count */
+       //msleep(20);   /* wait for L2 flush */
+#endif
        rdtsc_barrier();
        cycles1 = get_cycles();
        rdtsc_barrier();
@@ -94,7 +125,7 @@ static int my_open(struct inode *inode, struct file *file)
        cycles2 = get_cycles();
        rdtsc_barrier();
        local_irq_restore(flags);
-       printk("cycles : %llu\n", (cycles2-cycles1)/20000);
+       printk("cycles : %llu\n", cycles2-cycles1);
        return -EPERM;
 }