projects / lttng-ust.git / blame
| Commit | Line | Data |
|---|---|---|
| 1c196845 MJ |
1 | // SPDX-FileCopyrightText: 2021 Michael Jeanson <mjeanson@efficios.com> |
| 2 | // | |
| 3 | // SPDX-License-Identifier: MIT | |
| 2eba8e39 MJ |
4 | |
| 5 | #ifndef _LTTNG_UST_ARCH_H | |
| 6 | #define _LTTNG_UST_ARCH_H | |
| 7 | ||
| 8 | /* | |
| 9 | * Architecture detection using compiler defines. | |
| 10 | * | |
| 11 | * The following defines are used internally for architecture specific code. | |
| 12 | * | |
| 13 | * LTTNG_UST_ARCH_X86 : All x86 variants 32 and 64 bits | |
| 14 | * LTTNG_UST_ARCH_I386 : Specific to the i386 | |
| 15 | * LTTNG_UST_ARCH_AMD64 : All 64 bits x86 variants | |
| 16 | * LTTNG_UST_ARCH_K1OM : Specific to the Xeon Phi / MIC | |
| 17 | * | |
| 18 | * LTTNG_UST_ARCH_PPC : All PowerPC variants 32 and 64 bits | |
| 19 | * LTTNG_UST_ARCH_PPC64 : Specific to 64 bits variants | |
| 20 | * | |
| 21 | * LTTNG_UST_ARCH_S390 : All IBM s390 / s390x variants | |
| 22 | * | |
| 23 | * LTTNG_UST_ARCH_SPARC64 : All Sun SPARC variants | |
| 24 | * | |
| 25 | * LTTNG_UST_ARCH_ALPHA : All DEC Alpha variants | |
| 26 | * LTTNG_UST_ARCH_IA64 : All Intel Itanium variants | |
| 27 | * LTTNG_UST_ARCH_ARM : All ARM 32 bits variants | |
| 28 | * LTTNG_UST_ARCH_ARMV7 : All ARMv7 ISA variants | |
| 29 | * LTTNG_UST_ARCH_AARCH64 : All ARM 64 bits variants | |
| 30 | * LTTNG_UST_ARCH_MIPS : All MIPS variants | |
| 31 | * LTTNG_UST_ARCH_NIOS2 : All Intel / Altera NIOS II variants | |
| 32 | * LTTNG_UST_ARCH_TILE : All Tilera TILE variants | |
| 33 | * LTTNG_UST_ARCH_HPPA : All HP PA-RISC variants | |
| 34 | * LTTNG_UST_ARCH_M68K : All Motorola 68000 variants | |
| 35 | * LTTNG_UST_ARCH_RISCV : All RISC-V variants | |
| 36 | */ | |
| 37 | ||
| 38 | #if (defined(__INTEL_OFFLOAD) || defined(__TARGET_ARCH_MIC) || defined(__MIC__)) | |
| 39 | ||
| 40 | #define LTTNG_UST_ARCH_X86 1 | |
| 41 | #define LTTNG_UST_ARCH_AMD64 1 | |
| 42 | #define LTTNG_UST_ARCH_K1OM 1 | |
| 43 | ||
| 44 | #elif (defined(__amd64__) || defined(__amd64) || defined(__x86_64__) || defined(__x86_64)) | |
| 45 | ||
| 46 | #define LTTNG_UST_ARCH_X86 1 | |
| 47 | #define LTTNG_UST_ARCH_AMD64 1 | |
| 48 | ||
| 49 | #elif (defined(__i486__) || defined(__i586__) || defined(__i686__)) | |
| 50 | ||
| 51 | #define LTTNG_UST_ARCH_X86 1 | |
| 52 | ||
| 53 | #elif (defined(__i386__) || defined(__i386)) | |
| 54 | ||
| 55 | #define LTTNG_UST_ARCH_X86 1 | |
| 56 | #define LTTNG_UST_ARCH_I386 1 | |
| 57 | ||
| 58 | #elif (defined(__powerpc64__) || defined(__ppc64__)) | |
| 59 | ||
| 60 | #define LTTNG_UST_ARCH_PPC 1 | |
| 61 | #define LTTNG_UST_ARCH_PPC64 1 | |
| 62 | ||
| 63 | #elif (defined(__powerpc__) || defined(__powerpc) || defined(__ppc__)) | |
| 64 | ||
| 65 | #define LTTNG_UST_ARCH_PPC 1 | |
| 66 | ||
| 67 | #elif (defined(__s390__) || defined(__s390x__) || defined(__zarch__)) | |
| 68 | ||
| 69 | #define LTTNG_UST_ARCH_S390 1 | |
| 70 | ||
| 71 | #elif (defined(__sparc__) || defined(__sparc) || defined(__sparc64__)) | |
| 72 | ||
| 73 | #define LTTNG_UST_ARCH_SPARC64 1 | |
| 74 | ||
| 75 | #elif (defined(__alpha__) || defined(__alpha)) | |
| 76 | ||
| 77 | #define LTTNG_UST_ARCH_ALPHA 1 | |
| 78 | ||
| 79 | #elif (defined(__ia64__) || defined(__ia64)) | |
| 80 | ||
| 81 | #define LTTNG_UST_ARCH_IA64 1 | |
| 82 | ||
| 83 | #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7__)) | |
| 84 | ||
| 85 | #define LTTNG_UST_ARCH_ARMV7 1 | |
| 86 | #define LTTNG_UST_ARCH_ARM 1 | |
| 87 | ||
| 88 | #elif (defined(__arm__) || defined(__arm)) | |
| 89 | ||
| 90 | #define LTTNG_UST_ARCH_ARM 1 | |
| 91 | ||
| 92 | #elif defined(__aarch64__) | |
| 93 | ||
| 94 | #define LTTNG_UST_ARCH_AARCH64 1 | |
| 95 | ||
| 96 | #elif (defined(__mips__) || defined(__mips)) | |
| 97 | ||
| 98 | #define LTTNG_UST_ARCH_MIPS 1 | |
| 99 | ||
| 100 | #elif (defined(__nios2__) || defined(__nios2)) | |
| 101 | ||
| 102 | #define LTTNG_UST_ARCH_NIOS2 1 | |
| 103 | ||
| 104 | #elif (defined(__tile__) || defined(__tilegx__)) | |
| 105 | ||
| 106 | #define LTTNG_UST_ARCH_TILE 1 | |
| 107 | ||
| 108 | #elif (defined(__hppa__) || defined(__HPPA__) || defined(__hppa)) | |
| 109 | ||
| 110 | #define LTTNG_UST_ARCH_HPPA 1 | |
| 111 | ||
| 112 | #elif defined(__m68k__) | |
| 113 | ||
| 114 | #define LTTNG_UST_ARCH_M68K 1 | |
| 115 | ||
| 116 | #elif defined(__riscv) | |
| 117 | ||
| 118 | #define LTTNG_UST_ARCH_RISCV 1 | |
| 119 | ||
| 120 | #else | |
| 121 | ||
| 122 | /* Unrecognised architecture, use safe defaults */ | |
| 123 | #define LTTNG_UST_ARCH_UNKNOWN 1 | |
| 124 | ||
| 125 | #endif | |
| 126 | ||
| 127 | ||
| 128 | /* | |
| 129 | * Per architecture global settings. | |
| 130 | * | |
| 131 | * LTTNG_UST_ARCH_HAS_EFFICIENT_UNALIGNED_ACCESS: | |
| 132 | * The architecture has working and efficient unaligned memory access, the | |
| 133 | * content of the ringbuffers will packed instead of following the natural | |
| 134 | * alignment of the architecture. | |
| 135 | */ | |
| 136 | ||
| 137 | #if defined(LTTNG_UST_ARCH_X86) | |
| 138 | #define LTTNG_UST_ARCH_HAS_EFFICIENT_UNALIGNED_ACCESS 1 | |
| 139 | #endif | |
| 140 | ||
| 141 | #if defined(LTTNG_UST_ARCH_PPC) | |
| 142 | #define LTTNG_UST_ARCH_HAS_EFFICIENT_UNALIGNED_ACCESS 1 | |
| 143 | #endif | |
| 144 | ||
| 145 | #endif /* _LTTNG_UST_ARCH_H */ |