define sync_core for x86 PIC

Pushing/popping the reserved ebx register is surely less expensive
than a memory barrier.

Note that since ebx is a callee-save register, this is even safe for
signals (i.e. it would be safe even if we needed the value that cpuid
puts in %%ebx).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>

diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
index c4674de0d35adfbe3eaa19560ba3a4750583fecb..64cc026f9cd46343cb977dc7b076bf9a7d70a317 100644 (file)
--- a/urcu/arch_x86.h
+++ b/urcu/arch_x86.h
@@ -49,9 +49,13 @@ extern "C" {
 
 /*
  * Serialize core instruction execution. Also acts as a compiler barrier.
- * Cannot use cpuid on PIC because it clobbers the ebx register;
- * error: PIC register 'ebx' clobbered in 'asm'
+ * On PIC ebx cannot be clobbered
  */
+#ifdef __PIC__
+#define sync_core()                                                      \
+       asm volatile("push %%ebx; cpuid; pop %%ebx"                       \
+                    : : : "memory", "eax", "ecx", "edx");
+#endif
 #ifndef __PIC__
 #define sync_core()                                                      \
        asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");