static void pmc_flush_cache(void)
{
+ register int i;
/* write back and invalidate cache (a serializing instruction) */
__asm__ __volatile__ ( "wbinvd" : : : "memory" );
* Does wbinvd also cause the TLB to be flushed?
* A comment in mtrr.c suggests that it does.
*/
- { register int i; for (i = 0; i < 512*1024; i++) { } }
+
+ for (i = 0; i < 512*1024; i++) {
+ cpu_relax();
+ }
}
static inline void test(unsigned long arg, unsigned long arg2)
{
- register int temp[5];
+ volatile int temp[5];
#ifdef CACHEFLUSH
pmc_flush_cache();
#endif
static void pmc_flush_cache(void)
{
+ register int i;
/* write back and invalidate cache (a serializing instruction) */
__asm__ __volatile__ ( "wbinvd" : : : "memory" );
* Does wbinvd also cause the TLB to be flushed?
* A comment in mtrr.c suggests that it does.
*/
- { register int i; for (i = 0; i < 512*1024; i++) { } }
+ for (i = 0; i < 512*1024; i++) {
+ cpu_relax();
+ }
}
static inline void test(unsigned long arg, unsigned long arg2)
{
- register int temp[5];
+ volatile int temp[5];
#ifdef CACHEFLUSH
pmc_flush_cache();
#endif
static void pmc_flush_cache(void)
{
+ register int i;
/* write back and invalidate cache (a serializing instruction) */
__asm__ __volatile__ ( "wbinvd" : : : "memory" );
* Does wbinvd also cause the TLB to be flushed?
* A comment in mtrr.c suggests that it does.
*/
- { register int i; for (i = 0; i < 512*1024; i++) { } }
+ for (i = 0; i < 512*1024; i++) {
+ cpu_relax();
+ }
}
static inline void test(unsigned long arg, unsigned long arg2)
{
- register int temp[5];
+ volatile int temp[5];
#ifdef CACHEFLUSH
pmc_flush_cache();
#endif
static void pmc_flush_cache(void)
{
+ register int i;
/* write back and invalidate cache (a serializing instruction) */
__asm__ __volatile__ ( "wbinvd" : : : "memory" );
* Does wbinvd also cause the TLB to be flushed?
* A comment in mtrr.c suggests that it does.
*/
- { register int i; for (i = 0; i < 512*1024; i++) { } }
+ for (i = 0; i < 512*1024; i++) {
+ cpu_relax();
+ }
}
static inline void test(unsigned long arg, unsigned long arg2)
{
- register int temp[5];
+ volatile int temp[5];
#ifdef CACHEFLUSH
pmc_flush_cache();
#endif
#include <asm/system.h>
static void pmc_flush_cache(void)
- {
+{
+ register int i;
/* write back and invalidate cache (a serializing instruction) */
__asm__ __volatile__ ( "wbinvd" : : : "memory" );
* Does wbinvd also cause the TLB to be flushed?
* A comment in mtrr.c suggests that it does.
*/
- { register int i; for (i = 0; i < 512*1024; i++) { } }
- }
+ for (i = 0; i < 512*1024; i++) {
+ cpu_relax();
+ }
+}
static void noinline test2(const struct marker *mdata,
void *call_private, ...)
static inline void test(unsigned long arg, unsigned long arg2)
{
- register int temp[5];
+ volatile int temp[5];
#ifdef CACHEFLUSH
pmc_flush_cache();
#endif