X-Git-Url: https://git.lttng.org/?a=blobdiff_plain;ds=sidebyside;f=ltt%2Fbranches%2Fpoly%2Fdoc%2Fdeveloper%2Flttng-lttv-compatibility.html;h=60fa2187cc413b27b07dc14f587b4fe7f985eaa1;hb=0dee0e75e8a541ad435e9af431c426c53f155d71;hp=2cdbcb39acc92b18df8b74bae7d13ce6fd02a870;hpb=30a17b5380cf2b1fe0f9b2a1401274af9a3db651;p=lttv.git
diff --git a/ltt/branches/poly/doc/developer/lttng-lttv-compatibility.html b/ltt/branches/poly/doc/developer/lttng-lttv-compatibility.html
index 2cdbcb39..60fa2187 100644
--- a/ltt/branches/poly/doc/developer/lttng-lttv-compatibility.html
+++ b/ltt/branches/poly/doc/developer/lttng-lttv-compatibility.html
@@ -14,8 +14,14 @@ cellspacing="2">
LTTng
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+LTTng modules
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+Genevent
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Trace Major.Minor
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+Kernels-architectures
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Comments
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@@ -24,8 +30,18 @@ cellspacing="2">
0.4.4
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+0.3
+ |
+0.2
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0.4
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+
+2.6.12-rc4-mm2-i386 (tarball)
+2.6.12-rc4-i386 (git)
+2.6.9-i386 (contribution)
+2.6.9-x86_64 (contribution)
+ |
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@@ -34,11 +50,181 @@ cellspacing="2">
0.4.5
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+0.3
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+0.2
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0.5
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+2.6.12-rc4-i386 (git)
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Traces can now be written/read between 32 and 64 bits arch.
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+
+0.8.0
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+0.5.0
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+0.3
+ |
+0.3
+ |
+0.6
+ |
+
+2.6.12-rc4-i386 (git)
+2.6.12-i386 (git)
+2.6.13-i386 (git)
+ |
+
+ |
+
+
+0.8.0
+ |
+0.5.0
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+0.4
+ |
+0.3
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+0.6
+ |
+
+2.6.14-i386 (git)
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+
+ |
+
+
+0.8.0
+ |
+0.5.0a
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+0.4
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+0.3
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+0.6
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+
+2.6.14-i386 (tarball)
+ |
+
+ |
+
+
+
+
+0.8.1
+0.8.2
+0.8.3
+0.8.4
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+0.5.1
+ |
+0.4
+ |
+0.4
+ |
+0.6
+ |
+
+2.6.14-i386 (git)
+2.6.14-i386 (tarball)
+2.6.15-i386 (git)
+2.6.15-i386 (tarball)
+ |
+Per architecture syscall enumeration
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+
+
+
+
+0.8.1
+0.8.2
+0.8.3
+0.8.4
+ |
+
+0.5.3
+0.5.4
+0.5.5
+ |
+0.4
+ |
+
+0.4
+0.5
+ |
+0.6
+ |
+
+2.6.15-i386 (git)
+2.6.15-i386 (tarball)
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+APIC NMI watchdog can now be logged
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+
+
+
+
+0.8.5
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+
+0.5.6
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+0.4
+ |
+
+0.6
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+0.6
+ |
+
+2.6.15-i386 (git)
+2.6.15-i386 (tarball)
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+
+Custom write function in genevent (for process stack dump)
+Use atomic_cmpxchg()
+
+ |
+
+
+
+
+0.8.6
+ |
+
+0.5.7
+0.5.8
+0.5.9a
+0.5.10
+0.5.11
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+
+0.4
+ |
+
+0.6
+ |
+
+0.7
+ |
+
+2.6.15-i386 (git)
+2.6.15-i386 (tarball)
+ |
+
+Support for architectures without TSC.
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+ |
+
+
+
+