extern "C" {
#endif
-#define CONFIG_HAVE_MEM_COHERENCY
-
#define CACHE_LINE_SIZE 256
-#ifndef BITS_PER_LONG
-#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
-#endif
-
/*
* Inspired from the Linux kernel. Workaround Spitfire bug #51.
*/
#define rmb() membar_safe("#LoadLoad")
#define wmb() membar_safe("#StoreStore")
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb() mc()
- * #define rmb() rmc()
- * #define wmb() wmc()
- * #define mc() arch_cache_flush()
- * #define rmc() arch_cache_flush_read()
- * #define wmc() arch_cache_flush_write()
- */
-
-#define mc() barrier()
-#define rmc() barrier()
-#define wmc() barrier()
-
-#ifdef CONFIG_URCU_SMP
-#define smp_mb() mb()
-#define smp_rmb() rmb()
-#define smp_wmb() wmb()
-#define smp_mc() mc()
-#define smp_rmc() rmc()
-#define smp_wmc() wmc()
-#else
-#define smp_mb() barrier()
-#define smp_rmb() barrier()
-#define smp_wmb() barrier()
-#define smp_mc() barrier()
-#define smp_rmc() barrier()
-#define smp_wmc() barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void cpu_relax(void)
-{
- barrier();
-}
-
-/*
- * Serialize core instruction execution. Also acts as a compiler barrier.
- */
-static inline void sync_core()
-{
- mb();
-}
-
typedef unsigned long long cycles_t;
static inline cycles_t get_cycles (void)
}
#endif
+#include <urcu/arch_generic.h>
+
#endif /* _URCU_ARCH_SPARC64_H */