*/
#include <urcu/compiler.h>
-#include <urcu/arch_uatomic.h>
+#include "config.h"
#define CONFIG_HAVE_FENCE 1
#define CONFIG_HAVE_MEM_COHERENCY
+/* Include size of POWER5+ L3 cache lines: 256 bytes */
+#define CACHE_LINE_SIZE 256
+
#ifndef BITS_PER_LONG
#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
#endif
#define rmc() barrier()
#define wmc() barrier()
-/* Assume SMP machine, given we don't have this information */
-#define CONFIG_SMP 1
-
#ifdef CONFIG_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()