#include <urcu/arch.h>
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
/* hardcoded number of CPUs */
#define NR_CPUS 16384
for (;;) {
new = test_array_alloc();
new->a = 8;
- old = rcu_publish_content(&test_rcu_pointer, new);
+ old = rcu_xchg_pointer(&test_rcu_pointer, new);
+ synchronize_rcu();
if (old)
old->a = 0;
test_array_free(old);