<td style="vertical-align: top;">
0.34<br>
0.35<br>
+</td>
<td style="vertical-align: top;">
obsolete<br>
</td>
ltt-usertrace 0.27 fixes a signal race.<br>
LTTng 0.6.77 puts all process events in medium rate process channel.<br>
ltt-control 0.35 adds the Xen facility.<br>
+Matches LTTng for xen-unstable up to changeset: 14390.<br>
+</td>
<td style="vertical-align: top;">
ARM, mips, mipsel, powerpc64, i386, sparc64, m68k, ia64, s390, sparc, alpha.<br>
</td>
arm26, avr32, cris, frv, h8300, m32r, m68knommu, parisc, sh, sh64, um, v850,
xtensa.<br>
</td>
+</tr>
+
+<tr>
+<td style="vertical-align: top;">
+0.8.80<br>
+</td>
+<td style="vertical-align: top;">
+0.6.78<br>
+</td>
+<td style="vertical-align: top;">
+0.36<br>
+</td>
+<td style="vertical-align: top;">
+obsolete<br>
+</td>
+<td style="vertical-align: top;">
+0.28<br>
+</td>
+<td style="vertical-align: top;">
+0.33<br>
+</td>
+<td style="vertical-align: top;">
+0.8<br>
+</td>
+<td style="vertical-align: top;">
+2.6.20<br>
+ARM, MIPS32/64, powerpc32, powerpc64, ppc, i386, x86_64<br>
+</td>
+<td style="vertical-align: top;">
+Add compact channel.<br>
+Fix start of trace get full timestamp. Caused problems with time gap between
+trace create/start and 32 bits (or less) TSC in events.<br>
+Ok for xen-unstable changeset starting at 14391.<br>
+</td>
+<td style="vertical-align: top;">
+</td>
+<td style="vertical-align: top;">
+ARM, mips, mipsel, powerpc64, i386, sparc64, m68k, ia64, s390, sparc, alpha.<br>
+arm26, avr32, cris, frv, h8300, m32r, m68knommu, parisc, sh, sh64, um, v850,
+xtensa.<br>
+</td>
</tr>