-/* The "volatile" is due to gcc bugs */
-#define barrier() __asm__ __volatile__("": : :"memory")
-
-#define likely(x) __builtin_expect(!!(x), 1)
-#define unlikely(x) __builtin_expect(!!(x), 0)
-
-/*
- * Assume the architecture has coherent caches. Blackfin will want this unset.
- */
-#define CONFIG_HAVE_MEM_COHERENCY 1
-
-/* Assume P4 or newer */
-#define CONFIG_HAVE_FENCE 1
-
-/* Assume SMP machine, given we don't have this information */
-#define CONFIG_SMP 1
-
-
-#ifdef CONFIG_HAVE_MEM_COHERENCY
-/*
- * Caches are coherent, no need to flush them.
- */
-#define mc() barrier()
-#define rmc() barrier()
-#define wmc() barrier()
-#else
-#error "The architecture must create its own cache flush primitives"
-#define mc() arch_cache_flush()
-#define rmc() arch_cache_flush_read()
-#define wmc() arch_cache_flush_write()
-#endif
-
-
-#ifdef CONFIG_HAVE_MEM_COHERENCY
-
-/* x86 32/64 specific */
-#ifdef CONFIG_HAVE_FENCE
-#define mb() asm volatile("mfence":::"memory")
-#define rmb() asm volatile("lfence":::"memory")
-#define wmb() asm volatile("sfence"::: "memory")
-#else
-/*
- * Some non-Intel clones support out of order store. wmb() ceases to be a
- * nop for these.
- */
-#define mb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
-#define rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
-#define wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory")
-#endif
-
-#else /* !CONFIG_HAVE_MEM_COHERENCY */
-