40de9ff9909dc10327bb75e29aca9e33f7743f41
1 #ifndef _URCU_ARCH_UATOMIC_PPC_H
2 #define _URCU_ARCH_UATOMIC_PPC_H
5 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
6 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
7 * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
8 * Copyright (c) 2009 Mathieu Desnoyers
10 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
11 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
13 * Permission is hereby granted to use or copy this program
14 * for any purpose, provided the above notices are retained on all copies.
15 * Permission to modify the code and to distribute modified code is granted,
16 * provided the above notices are retained, and a notice that the code was
17 * modified is included with the above copyright notice.
19 * Code inspired from libuatomic_ops-1.2, inherited in part from the
20 * Boehm-Demers-Weiser conservative garbage collector.
23 #include <urcu/compiler.h>
25 #ifndef __SIZEOF_LONG__
27 #define __SIZEOF_LONG__ 8
29 #define __SIZEOF_LONG__ 4
34 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
37 #define ILLEGAL_INSTR ".long 0xd00d00"
39 #define uatomic_set(addr, v) \
41 ACCESS_ONCE(*(addr)) = (v); \
44 #define uatomic_read(addr) ACCESS_ONCE(*(addr))
47 * Using a isync as second barrier for exchange to provide acquire semantic.
48 * According to uatomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
49 * explicit that this also has acquire semantics."
50 * Derived from AO_compare_and_swap(), but removed the comparison.
55 static inline __attribute__((always_inline
))
56 unsigned long _uatomic_exchange(void *addr
, unsigned long val
, int len
)
65 "1:\t" "lwarx %0,0,%1\n" /* load and reserve */
66 "stwcx. %2,0,%1\n" /* else store conditional */
67 "bne- 1b\n" /* retry if lost reservation */
75 #if (BITS_PER_LONG == 64)
82 "1:\t" "ldarx %0,0,%1\n" /* load and reserve */
83 "stdcx. %2,0,%1\n" /* else store conditional */
84 "bne- 1b\n" /* retry if lost reservation */
94 /* generate an illegal instruction. Cannot catch this with linker tricks
95 * when optimizations are disabled. */
96 __asm__
__volatile__(ILLEGAL_INSTR
);
100 #define uatomic_xchg(addr, v) \
101 ((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
105 static inline __attribute__((always_inline
))
106 unsigned long _uatomic_cmpxchg(void *addr
, unsigned long old
,
107 unsigned long _new
, int len
)
112 unsigned int old_val
;
114 __asm__
__volatile__(
116 "1:\t" "lwarx %0,0,%1\n" /* load and reserve */
117 "cmpd %0,%3\n" /* if load is not equal to */
118 "bne 2f\n" /* old, fail */
119 "stwcx. %2,0,%1\n" /* else store conditional */
120 "bne- 1b\n" /* retry if lost reservation */
124 : "r"(addr
), "r"((unsigned int)_new
),
125 "r"((unsigned int)old
)
130 #if (BITS_PER_LONG == 64)
133 unsigned long old_val
;
135 __asm__
__volatile__(
137 "1:\t" "ldarx %0,0,%1\n" /* load and reserve */
138 "cmpd %0,%3\n" /* if load is not equal to */
139 "bne 2f\n" /* old, fail */
140 "stdcx. %2,0,%1\n" /* else store conditional */
141 "bne- 1b\n" /* retry if lost reservation */
145 : "r"(addr
), "r"((unsigned long)_new
),
146 "r"((unsigned long)old
)
153 /* generate an illegal instruction. Cannot catch this with linker tricks
154 * when optimizations are disabled. */
155 __asm__
__volatile__(ILLEGAL_INSTR
);
160 #define uatomic_cmpxchg(addr, old, _new) \
161 ((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\
162 (unsigned long)(_new), \
165 /* uatomic_add_return */
167 static inline __attribute__((always_inline
))
168 unsigned long _uatomic_add_return(void *addr
, unsigned long val
,
176 __asm__
__volatile__(
178 "1:\t" "lwarx %0,0,%1\n" /* load and reserve */
179 "add %0,%2,%0\n" /* add val to value loaded */
180 "stwcx. %0,0,%1\n" /* store conditional */
181 "bne- 1b\n" /* retry if lost reservation */
184 : "r"(addr
), "r"(val
)
189 #if (BITS_PER_LONG == 64)
192 unsigned long result
;
194 __asm__
__volatile__(
196 "1:\t" "ldarx %0,0,%1\n" /* load and reserve */
197 "add %0,%2,%0\n" /* add val to value loaded */
198 "stdcx. %0,0,%1\n" /* store conditional */
199 "bne- 1b\n" /* retry if lost reservation */
202 : "r"(addr
), "r"(val
)
209 /* generate an illegal instruction. Cannot catch this with linker tricks
210 * when optimizations are disabled. */
211 __asm__
__volatile__(ILLEGAL_INSTR
);
216 #define uatomic_add_return(addr, v) \
217 ((__typeof__(*(addr))) _uatomic_add_return((addr), \
218 (unsigned long)(v), \
221 /* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */
223 #define uatomic_sub_return(addr, v) uatomic_add_return((addr), -(v))
225 #define uatomic_add(addr, v) (void)uatomic_add_return((addr), (v))
226 #define uatomic_sub(addr, v) (void)uatomic_sub_return((addr), (v))
228 #define uatomic_inc(addr) uatomic_add((addr), 1)
229 #define uatomic_dec(addr) uatomic_add((addr), -1)
231 #endif /* _URCU_ARCH_UATOMIC_PPC_H */
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