1 #ifndef _URCU_ARCH_PPC_H
2 #define _URCU_ARCH_PPC_H
5 * arch_ppc.h: trivial definitions for the powerpc architecture.
7 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
8 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2.1 of the License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
25 #include <urcu/compiler.h>
28 #define CONFIG_HAVE_FENCE 1
29 #define CONFIG_HAVE_MEM_COHERENCY
31 /* Include size of POWER5+ L3 cache lines: 256 bytes */
32 #define CACHE_LINE_SIZE 256
35 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
38 #define mb() asm volatile("sync":::"memory")
39 #define rmb() asm volatile("sync":::"memory")
40 #define wmb() asm volatile("sync"::: "memory")
43 * Architectures without cache coherency need something like the following:
48 * #define mc() arch_cache_flush()
49 * #define rmc() arch_cache_flush_read()
50 * #define wmc() arch_cache_flush_write()
53 #define mc() barrier()
54 #define rmc() barrier()
55 #define wmc() barrier()
59 #define smp_rmb() rmb()
60 #define smp_wmb() wmb()
62 #define smp_rmc() rmc()
63 #define smp_wmc() wmc()
65 #define smp_mb() barrier()
66 #define smp_rmb() barrier()
67 #define smp_wmb() barrier()
68 #define smp_mc() barrier()
69 #define smp_rmc() barrier()
70 #define smp_wmc() barrier()
73 /* Nop everywhere except on alpha. */
74 #define smp_read_barrier_depends()
76 static inline void cpu_relax(void)
82 * Serialize core instruction execution. Also acts as a compiler barrier.
84 static inline void sync_core()
86 asm volatile("isync" : : : "memory");
92 asm volatile("mftbl %0" : "=r" (rval)); \
99 asm volatile("mftbu %0" : "=r" (rval)); \
103 typedef unsigned long long cycles_t
;
105 static inline cycles_t
get_cycles (void)
115 return (((cycles_t
) h
) << 32) + l
;
119 #endif /* _URCU_ARCH_PPC_H */
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