X-Git-Url: https://git.lttng.org/?p=urcu.git;a=blobdiff_plain;f=urcu%2Farch_x86.h;h=d0a58e80caa5abfc980a58ad51407f82b0ceeee6;hp=aad541e90e089edcb7f962e94a0c1ae58f7f5e5c;hb=5481ddb381061bda64aebc039900d21cac6a6caf;hpb=21c0a9849be7342dbe4ea717cc1785bd133d5367

diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
index aad541e..d0a58e8 100644
--- a/urcu/arch_x86.h
+++ b/urcu/arch_x86.h
@@ -32,17 +32,17 @@ extern "C" {
 #define CACHE_LINE_SIZE	128
 
 #ifdef CONFIG_RCU_HAVE_FENCE
-#define mb()    asm volatile("mfence":::"memory")
-#define rmb()   asm volatile("lfence":::"memory")
-#define wmb()   asm volatile("sfence"::: "memory")
+#define cmm_mb()    asm volatile("mfence":::"memory")
+#define cmm_rmb()   asm volatile("lfence":::"memory")
+#define cmm_wmb()   asm volatile("sfence"::: "memory")
 #else
 /*
- * Some non-Intel clones support out of order store. wmb() ceases to be a
+ * Some non-Intel clones support out of order store. cmm_wmb() ceases to be a
  * nop for these.
  */
-#define mb()    asm volatile("lock; addl $0,0(%%esp)":::"memory")
-#define rmb()   asm volatile("lock; addl $0,0(%%esp)":::"memory")
-#define wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
+#define cmm_mb()    asm volatile("lock; addl $0,0(%%esp)":::"memory")
+#define cmm_rmb()   asm volatile("lock; addl $0,0(%%esp)":::"memory")
+#define cmm_wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
 #endif
 
 #define cpu_relax()	asm volatile("rep; nop" : : : "memory");