X-Git-Url: https://git.lttng.org/?p=urcu.git;a=blobdiff_plain;f=urcu.h;h=a32fb94247fcfa11e4f5330d5e278821ab3a1e04;hp=01a4c6857d7e6fd31668dec57615be03e94ccc91;hb=69a757c902c0cfb6245da18339b297b9ca6f94e0;hpb=1430ee0bdca4cb454d534ef7fc84af3e0692f26b diff --git a/urcu.h b/urcu.h index 01a4c68..a32fb94 100644 --- a/urcu.h +++ b/urcu.h @@ -17,11 +17,16 @@ * Distributed under GPLv2 */ +#define __USE_GNU #include +#include /* The "volatile" is due to gcc bugs */ #define barrier() __asm__ __volatile__("": : :"memory") +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) + /* x86 32/64 specific */ #define mb() asm volatile("mfence":::"memory") #define rmb() asm volatile("lfence":::"memory") @@ -33,6 +38,51 @@ static inline void atomic_inc(int *v) : "+m" (*v)); } +#define xchg(ptr, v) \ + ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), sizeof(*(ptr)))) + +struct __xchg_dummy { + unsigned long a[100]; +}; +#define __xg(x) ((struct __xchg_dummy *)(x)) + +/* + * Note: no "lock" prefix even on SMP: xchg always implies lock anyway + * Note 2: xchg has side effect, so that attribute volatile is necessary, + * but generally the primitive is invalid, *ptr is output argument. --ANK + */ +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, + int size) +{ + switch (size) { + case 1: + asm volatile("xchgb %b0,%1" + : "=q" (x) + : "m" (*__xg(ptr)), "0" (x) + : "memory"); + break; + case 2: + asm volatile("xchgw %w0,%1" + : "=r" (x) + : "m" (*__xg(ptr)), "0" (x) + : "memory"); + break; + case 4: + asm volatile("xchgl %k0,%1" + : "=r" (x) + : "m" (*__xg(ptr)), "0" (x) + : "memory"); + break; + case 8: + asm volatile("xchgq %0,%1" + : "=r" (x) + : "m" (*__xg(ptr)), "0" (x) + : "memory"); + break; + } + return x; +} + /* Nop everywhere except on alpha. */ #define smp_read_barrier_depends() @@ -70,6 +120,8 @@ static inline void atomic_inc(int *v) #ifdef DEBUG_YIELD #include +#include +#include #define YIELD_READ (1 << 0) #define YIELD_WRITE (1 << 1) @@ -118,7 +170,11 @@ static inline void debug_yield_init(void) #define RCU_GP_CTR_BIT (1U << 8) #define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) -/* Global quiescent period counter with low-order bits unused. */ +/* + * Global quiescent period counter with low-order bits unused. + * Using a int rather than a char to eliminate false register dependencies + * causing stalls on some architectures. + */ extern int urcu_gp_ctr; extern int __thread urcu_active_readers; @@ -143,7 +199,7 @@ static inline void rcu_read_lock(void) debug_yield_read(); tmp = urcu_active_readers; debug_yield_read(); - if (!(tmp & RCU_GP_CTR_NEST_MASK)) + if (likely(!(tmp & RCU_GP_CTR_NEST_MASK))) urcu_active_readers = urcu_gp_ctr + RCU_GP_COUNT; else urcu_active_readers = tmp + RCU_GP_COUNT; @@ -169,7 +225,49 @@ static inline void rcu_read_unlock(void) debug_yield_read(); } -extern void *urcu_publish_content(void **ptr, void *new); +/** + * rcu_assign_pointer - assign (publicize) a pointer to a newly + * initialized structure that will be dereferenced by RCU read-side + * critical sections. Returns the value assigned. + * + * Inserts memory barriers on architectures that require them + * (pretty much all of them other than x86), and also prevents + * the compiler from reordering the code that initializes the + * structure after the pointer assignment. More importantly, this + * call documents which pointers will be dereferenced by RCU read-side + * code. + */ + +#define rcu_assign_pointer(p, v) \ + ({ \ + if (!__builtin_constant_p(v) || \ + ((v) != NULL)) \ + wmb(); \ + (p) = (v); \ + }) + +#define rcu_xchg_pointer(p, v) \ + ({ \ + if (!__builtin_constant_p(v) || \ + ((v) != NULL)) \ + wmb(); \ + xchg(p, v); \ + }) + +extern void synchronize_rcu(void); + +/* + * Exchanges the pointer and waits for quiescent state. + * The pointer returned can be freed. + */ +#define urcu_publish_content(p, v) \ + ({ \ + void *oldptr; \ + debug_yield_write(); \ + oldptr = rcu_xchg_pointer(p, v); \ + synchronize_rcu(); \ + oldptr; \ + }) /* * Reader thread registration.