X-Git-Url: https://git.lttng.org/?p=urcu.git;a=blobdiff_plain;f=tests%2Ftest_qsbr.c;h=5284a4837bc9fdd0e69e28db4bbec6774ae0e67a;hp=cf2fec2a8cbc8ce19f366ce669412bf3842ef5f5;hb=94b343fd8d68512d78d8646c646c15a1b3f84186;hpb=ec4e58a3aba2084440012f8ccac3a31eb6101183 diff --git a/tests/test_qsbr.c b/tests/test_qsbr.c index cf2fec2..5284a48 100644 --- a/tests/test_qsbr.c +++ b/tests/test_qsbr.c @@ -32,12 +32,10 @@ #include #include #include +#include #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - /* hardcoded number of CPUs */ #define NR_CPUS 16384 @@ -262,7 +260,8 @@ void *thr_writer(void *_count) for (;;) { new = test_array_alloc(); new->a = 8; - old = rcu_publish_content(&test_rcu_pointer, new); + old = rcu_xchg_pointer(&test_rcu_pointer, new); + synchronize_rcu(); /* can be done after unlock */ if (old) old->a = 0;