Rename all arch primitives with prefix caa_

[urcu.git] / urcu / arch_x86.h

diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
index aad541e90e089edcb7f962e94a0c1ae58f7f5e5c..20db5cfff98466c528800b37f986eaf3efaad689 100644 (file)
--- a/urcu/arch_x86.h
+++ b/urcu/arch_x86.h
@@ -29,23 +29,23 @@
 extern "C" {
 #endif 
 
-#define CACHE_LINE_SIZE        128
+#define CAA_CACHE_LINE_SIZE    128
 
 #ifdef CONFIG_RCU_HAVE_FENCE
-#define mb()    asm volatile("mfence":::"memory")
-#define rmb()   asm volatile("lfence":::"memory")
-#define wmb()   asm volatile("sfence"::: "memory")
+#define cmm_mb()    asm volatile("mfence":::"memory")
+#define cmm_rmb()   asm volatile("lfence":::"memory")
+#define cmm_wmb()   asm volatile("sfence"::: "memory")
 #else
 /*
- * Some non-Intel clones support out of order store. wmb() ceases to be a
+ * Some non-Intel clones support out of order store. cmm_wmb() ceases to be a
  * nop for these.
  */
-#define mb()    asm volatile("lock; addl $0,0(%%esp)":::"memory")
-#define rmb()   asm volatile("lock; addl $0,0(%%esp)":::"memory")
-#define wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
+#define cmm_mb()    asm volatile("lock; addl $0,0(%%esp)":::"memory")
+#define cmm_rmb()   asm volatile("lock; addl $0,0(%%esp)":::"memory")
+#define cmm_wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
 #endif
 
-#define cpu_relax()    asm volatile("rep; nop" : : : "memory");
+#define caa_cpu_relax()        asm volatile("rep; nop" : : : "memory");
 
 #define rdtscll(val)                                                     \
        do {                                                              \
@@ -57,7 +57,7 @@ extern "C" {
 
 typedef unsigned long long cycles_t;
 
-static inline cycles_t get_cycles(void)
+static inline cycles_t caa_get_cycles(void)
 {
         cycles_t ret = 0;