projects / lttng-ust.git / blame
| Commit | Line | Data |
|---|---|---|
| 2eba8e39 MJ |
1 | /* |
| 2 | * SPDX-License-Identifier: MIT | |
| 3 | * | |
| 4 | * Copyright (C) 2021 Michael Jeanson <michael.jeanson@efficios.com> | |
| 5 | * | |
| 6 | */ | |
| 7 | ||
| 8 | #ifndef _LTTNG_UST_ARCH_H | |
| 9 | #define _LTTNG_UST_ARCH_H | |
| 10 | ||
| 11 | /* | |
| 12 | * Architecture detection using compiler defines. | |
| 13 | * | |
| 14 | * The following defines are used internally for architecture specific code. | |
| 15 | * | |
| 16 | * LTTNG_UST_ARCH_X86 : All x86 variants 32 and 64 bits | |
| 17 | * LTTNG_UST_ARCH_I386 : Specific to the i386 | |
| 18 | * LTTNG_UST_ARCH_AMD64 : All 64 bits x86 variants | |
| 19 | * LTTNG_UST_ARCH_K1OM : Specific to the Xeon Phi / MIC | |
| 20 | * | |
| 21 | * LTTNG_UST_ARCH_PPC : All PowerPC variants 32 and 64 bits | |
| 22 | * LTTNG_UST_ARCH_PPC64 : Specific to 64 bits variants | |
| 23 | * | |
| 24 | * LTTNG_UST_ARCH_S390 : All IBM s390 / s390x variants | |
| 25 | * | |
| 26 | * LTTNG_UST_ARCH_SPARC64 : All Sun SPARC variants | |
| 27 | * | |
| 28 | * LTTNG_UST_ARCH_ALPHA : All DEC Alpha variants | |
| 29 | * LTTNG_UST_ARCH_IA64 : All Intel Itanium variants | |
| 30 | * LTTNG_UST_ARCH_ARM : All ARM 32 bits variants | |
| 31 | * LTTNG_UST_ARCH_ARMV7 : All ARMv7 ISA variants | |
| 32 | * LTTNG_UST_ARCH_AARCH64 : All ARM 64 bits variants | |
| 33 | * LTTNG_UST_ARCH_MIPS : All MIPS variants | |
| 34 | * LTTNG_UST_ARCH_NIOS2 : All Intel / Altera NIOS II variants | |
| 35 | * LTTNG_UST_ARCH_TILE : All Tilera TILE variants | |
| 36 | * LTTNG_UST_ARCH_HPPA : All HP PA-RISC variants | |
| 37 | * LTTNG_UST_ARCH_M68K : All Motorola 68000 variants | |
| 38 | * LTTNG_UST_ARCH_RISCV : All RISC-V variants | |
| 39 | */ | |
| 40 | ||
| 41 | #if (defined(__INTEL_OFFLOAD) || defined(__TARGET_ARCH_MIC) || defined(__MIC__)) | |
| 42 | ||
| 43 | #define LTTNG_UST_ARCH_X86 1 | |
| 44 | #define LTTNG_UST_ARCH_AMD64 1 | |
| 45 | #define LTTNG_UST_ARCH_K1OM 1 | |
| 46 | ||
| 47 | #elif (defined(__amd64__) || defined(__amd64) || defined(__x86_64__) || defined(__x86_64)) | |
| 48 | ||
| 49 | #define LTTNG_UST_ARCH_X86 1 | |
| 50 | #define LTTNG_UST_ARCH_AMD64 1 | |
| 51 | ||
| 52 | #elif (defined(__i486__) || defined(__i586__) || defined(__i686__)) | |
| 53 | ||
| 54 | #define LTTNG_UST_ARCH_X86 1 | |
| 55 | ||
| 56 | #elif (defined(__i386__) || defined(__i386)) | |
| 57 | ||
| 58 | #define LTTNG_UST_ARCH_X86 1 | |
| 59 | #define LTTNG_UST_ARCH_I386 1 | |
| 60 | ||
| 61 | #elif (defined(__powerpc64__) || defined(__ppc64__)) | |
| 62 | ||
| 63 | #define LTTNG_UST_ARCH_PPC 1 | |
| 64 | #define LTTNG_UST_ARCH_PPC64 1 | |
| 65 | ||
| 66 | #elif (defined(__powerpc__) || defined(__powerpc) || defined(__ppc__)) | |
| 67 | ||
| 68 | #define LTTNG_UST_ARCH_PPC 1 | |
| 69 | ||
| 70 | #elif (defined(__s390__) || defined(__s390x__) || defined(__zarch__)) | |
| 71 | ||
| 72 | #define LTTNG_UST_ARCH_S390 1 | |
| 73 | ||
| 74 | #elif (defined(__sparc__) || defined(__sparc) || defined(__sparc64__)) | |
| 75 | ||
| 76 | #define LTTNG_UST_ARCH_SPARC64 1 | |
| 77 | ||
| 78 | #elif (defined(__alpha__) || defined(__alpha)) | |
| 79 | ||
| 80 | #define LTTNG_UST_ARCH_ALPHA 1 | |
| 81 | ||
| 82 | #elif (defined(__ia64__) || defined(__ia64)) | |
| 83 | ||
| 84 | #define LTTNG_UST_ARCH_IA64 1 | |
| 85 | ||
| 86 | #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7__)) | |
| 87 | ||
| 88 | #define LTTNG_UST_ARCH_ARMV7 1 | |
| 89 | #define LTTNG_UST_ARCH_ARM 1 | |
| 90 | ||
| 91 | #elif (defined(__arm__) || defined(__arm)) | |
| 92 | ||
| 93 | #define LTTNG_UST_ARCH_ARM 1 | |
| 94 | ||
| 95 | #elif defined(__aarch64__) | |
| 96 | ||
| 97 | #define LTTNG_UST_ARCH_AARCH64 1 | |
| 98 | ||
| 99 | #elif (defined(__mips__) || defined(__mips)) | |
| 100 | ||
| 101 | #define LTTNG_UST_ARCH_MIPS 1 | |
| 102 | ||
| 103 | #elif (defined(__nios2__) || defined(__nios2)) | |
| 104 | ||
| 105 | #define LTTNG_UST_ARCH_NIOS2 1 | |
| 106 | ||
| 107 | #elif (defined(__tile__) || defined(__tilegx__)) | |
| 108 | ||
| 109 | #define LTTNG_UST_ARCH_TILE 1 | |
| 110 | ||
| 111 | #elif (defined(__hppa__) || defined(__HPPA__) || defined(__hppa)) | |
| 112 | ||
| 113 | #define LTTNG_UST_ARCH_HPPA 1 | |
| 114 | ||
| 115 | #elif defined(__m68k__) | |
| 116 | ||
| 117 | #define LTTNG_UST_ARCH_M68K 1 | |
| 118 | ||
| 119 | #elif defined(__riscv) | |
| 120 | ||
| 121 | #define LTTNG_UST_ARCH_RISCV 1 | |
| 122 | ||
| 123 | #else | |
| 124 | ||
| 125 | /* Unrecognised architecture, use safe defaults */ | |
| 126 | #define LTTNG_UST_ARCH_UNKNOWN 1 | |
| 127 | ||
| 128 | #endif | |
| 129 | ||
| 130 | ||
| 131 | /* | |
| 132 | * Per architecture global settings. | |
| 133 | * | |
| 134 | * LTTNG_UST_ARCH_HAS_EFFICIENT_UNALIGNED_ACCESS: | |
| 135 | * The architecture has working and efficient unaligned memory access, the | |
| 136 | * content of the ringbuffers will packed instead of following the natural | |
| 137 | * alignment of the architecture. | |
| 138 | */ | |
| 139 | ||
| 140 | #if defined(LTTNG_UST_ARCH_X86) | |
| 141 | #define LTTNG_UST_ARCH_HAS_EFFICIENT_UNALIGNED_ACCESS 1 | |
| 142 | #endif | |
| 143 | ||
| 144 | #if defined(LTTNG_UST_ARCH_PPC) | |
| 145 | #define LTTNG_UST_ARCH_HAS_EFFICIENT_UNALIGNED_ACCESS 1 | |
| 146 | #endif | |
| 147 | ||
| 148 | #endif /* _LTTNG_UST_ARCH_H */ |