X-Git-Url: https://git.lttng.org/?a=blobdiff_plain;f=urcu.h;h=2e8c0424abb0d413b6a64035ba05acced231d253;hb=581a270d427d9598c06a4da9ae7f9a9fc5354ec0;hp=bc86d435845d6da33255a63d7d5d2fbdecb4aa76;hpb=9b171f4656b61d023c327af3d0b4de22eee37353;p=urcu.git

diff --git a/urcu.h b/urcu.h
index bc86d43..2e8c042 100644
--- a/urcu.h
+++ b/urcu.h
@@ -17,12 +17,15 @@
  * Distributed under GPLv2
  */
 
-#define __USE_GNU
 #include <stdlib.h>
+#include <pthread.h>
 
 /* The "volatile" is due to gcc bugs */
 #define barrier() __asm__ __volatile__("": : :"memory")
 
+#define likely(x)       __builtin_expect(!!(x), 1)
+#define unlikely(x)     __builtin_expect(!!(x), 0)
+
 /* x86 32/64 specific */
 #define mb()    asm volatile("mfence":::"memory")
 #define rmb()   asm volatile("lfence":::"memory")
@@ -64,7 +67,13 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
 			     : "memory");
 		break;
 	case 4:
-		asm volatile("xchgl %0,%1"
+		asm volatile("xchgl %k0,%1"
+			     : "=r" (x)
+			     : "m" (*__xg(ptr)), "0" (x)
+			     : "memory");
+		break;
+	case 8:
+		asm volatile("xchgq %0,%1"
 			     : "=r" (x)
 			     : "m" (*__xg(ptr)), "0" (x)
 			     : "memory");
@@ -160,7 +169,11 @@ static inline void debug_yield_init(void)
 #define RCU_GP_CTR_BIT		(1U << 8)
 #define RCU_GP_CTR_NEST_MASK	(RCU_GP_CTR_BIT - 1)
 
-/* Global quiescent period counter with low-order bits unused. */
+/*
+ * Global quiescent period counter with low-order bits unused.
+ * Using a int rather than a char to eliminate false register dependencies
+ * causing stalls on some architectures.
+ */
 extern int urcu_gp_ctr;
 
 extern int __thread urcu_active_readers;
@@ -185,7 +198,7 @@ static inline void rcu_read_lock(void)
 	debug_yield_read();
 	tmp = urcu_active_readers;
 	debug_yield_read();
-	if (!(tmp & RCU_GP_CTR_NEST_MASK))
+	if (likely(!(tmp & RCU_GP_CTR_NEST_MASK)))
 		urcu_active_readers = urcu_gp_ctr + RCU_GP_COUNT;
 	else
 		urcu_active_readers = tmp + RCU_GP_COUNT;