X-Git-Url: https://git.lttng.org/?a=blobdiff_plain;f=urcu%2Fuatomic_arch_x86.h;h=9fedee65fac00d72a95545b2bcd38c909a786d30;hb=bf33aaea06cbf8257cc49c38abca6d26c0c31c78;hp=09a5bbbbfa0f98fa1b7b840a06fc5e4dde5e1dbf;hpb=28ca843d76e4fdc88dc51c4ae444d41446158e83;p=urcu.git

diff --git a/urcu/uatomic_arch_x86.h b/urcu/uatomic_arch_x86.h
index 09a5bbb..9fedee6 100644
--- a/urcu/uatomic_arch_x86.h
+++ b/urcu/uatomic_arch_x86.h
@@ -231,6 +231,114 @@ unsigned long __uatomic_add_return(void *addr, unsigned long val,
 						  (unsigned long)(v),	\
 						  sizeof(*(addr))))
 
+/* uatomic_and */
+
+static inline __attribute__((always_inline))
+void __uatomic_and(void *addr, unsigned long val, int len)
+{
+	switch (len) {
+	case 1:
+	{
+		__asm__ __volatile__(
+		"lock; andb %1, %0"
+			: "=m"(*__hp(addr))
+			: "iq" ((unsigned char)val)
+			: "memory");
+		return;
+	}
+	case 2:
+	{
+		__asm__ __volatile__(
+		"lock; andw %1, %0"
+			: "=m"(*__hp(addr))
+			: "ir" ((unsigned short)val)
+			: "memory");
+		return;
+	}
+	case 4:
+	{
+		__asm__ __volatile__(
+		"lock; andl %1, %0"
+			: "=m"(*__hp(addr))
+			: "ir" ((unsigned int)val)
+			: "memory");
+		return;
+	}
+#if (CAA_BITS_PER_LONG == 64)
+	case 8:
+	{
+		__asm__ __volatile__(
+		"lock; andq %1, %0"
+			: "=m"(*__hp(addr))
+			: "er" ((unsigned long)val)
+			: "memory");
+		return;
+	}
+#endif
+	}
+	/* generate an illegal instruction. Cannot catch this with linker tricks
+	 * when optimizations are disabled. */
+	__asm__ __volatile__("ud2");
+	return;
+}
+
+#define _uatomic_and(addr, v)						   \
+	(__uatomic_and((addr), (unsigned long)(v), sizeof(*(addr))))
+
+/* uatomic_or */
+
+static inline __attribute__((always_inline))
+void __uatomic_or(void *addr, unsigned long val, int len)
+{
+	switch (len) {
+	case 1:
+	{
+		__asm__ __volatile__(
+		"lock; orb %1, %0"
+			: "=m"(*__hp(addr))
+			: "iq" ((unsigned char)val)
+			: "memory");
+		return;
+	}
+	case 2:
+	{
+		__asm__ __volatile__(
+		"lock; orw %1, %0"
+			: "=m"(*__hp(addr))
+			: "ir" ((unsigned short)val)
+			: "memory");
+		return;
+	}
+	case 4:
+	{
+		__asm__ __volatile__(
+		"lock; orl %1, %0"
+			: "=m"(*__hp(addr))
+			: "ir" ((unsigned int)val)
+			: "memory");
+		return;
+	}
+#if (CAA_BITS_PER_LONG == 64)
+	case 8:
+	{
+		__asm__ __volatile__(
+		"lock; orq %1, %0"
+			: "=m"(*__hp(addr))
+			: "er" ((unsigned long)val)
+			: "memory");
+		return;
+	}
+#endif
+	}
+	/* generate an illegal instruction. Cannot catch this with linker tricks
+	 * when optimizations are disabled. */
+	__asm__ __volatile__("ud2");
+	return;
+}
+
+#define _uatomic_or(addr, v)						   \
+	(__uatomic_or((addr), (unsigned long)(v), sizeof(*(addr))))
+
 /* uatomic_add */
 
 static inline __attribute__((always_inline))
@@ -428,6 +536,20 @@ extern unsigned long _compat_uatomic_cmpxchg(void *addr, unsigned long old,
 						(unsigned long)(_new), 	       \
 						sizeof(*(addr))))
 
+extern unsigned long _compat_uatomic_and(void *addr,
+				         unsigned long _new, int len);
+#define compat_uatomic_and(addr, v)				       \
+	((__typeof__(*(addr))) _compat_uatomic_and((addr),	       \
+						   (unsigned long)(v), \
+						   sizeof(*(addr))))
+
+extern unsigned long _compat_uatomic_or(void *addr,
+				        unsigned long _new, int len);
+#define compat_uatomic_or(addr, v)				       \
+	((__typeof__(*(addr))) _compat_uatomic_or((addr),	       \
+						  (unsigned long)(v),  \
+						  sizeof(*(addr))))
+
 extern unsigned long _compat_uatomic_add_return(void *addr,
 						unsigned long _new, int len);
 #define compat_uatomic_add_return(addr, v)				       \
@@ -454,6 +576,10 @@ extern unsigned long _compat_uatomic_add_return(void *addr,
 		UATOMIC_COMPAT(cmpxchg(addr, old, _new))
 #define uatomic_xchg(addr, v)			\
 		UATOMIC_COMPAT(xchg(addr, v))
+#define uatomic_and(addr, v)		\
+		UATOMIC_COMPAT(and(addr, v))
+#define uatomic_or(addr, v)		\
+		UATOMIC_COMPAT(or(addr, v))
 #define uatomic_add_return(addr, v)		\
 		UATOMIC_COMPAT(add_return(addr, v))