X-Git-Url: https://git.lttng.org/?a=blobdiff_plain;f=tests%2Ftest_qsbr_gc.c;h=97660676e548f08d55cc7b3aadf51c066c03338d;hb=40646e1ec30a2fa5d289175643c1d1343e2f9b77;hp=d32d1a04175159bc186aeb9f3fbf6f98e98a837a;hpb=ec4e58a3aba2084440012f8ccac3a31eb6101183;p=urcu.git

diff --git a/tests/test_qsbr_gc.c b/tests/test_qsbr_gc.c
index d32d1a0..9766067 100644
--- a/tests/test_qsbr_gc.c
+++ b/tests/test_qsbr_gc.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384