X-Git-Url: https://git.lttng.org/?a=blobdiff_plain;f=tests%2Ftest_qsbr.c;h=d6c4d1aed017420666da1ad68562542f151b6d80;hb=40646e1ec30a2fa5d289175643c1d1343e2f9b77;hp=cf2fec2a8cbc8ce19f366ce669412bf3842ef5f5;hpb=ec4e58a3aba2084440012f8ccac3a31eb6101183;p=urcu.git

diff --git a/tests/test_qsbr.c b/tests/test_qsbr.c
index cf2fec2..d6c4d1a 100644
--- a/tests/test_qsbr.c
+++ b/tests/test_qsbr.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 
@@ -262,7 +259,8 @@ void *thr_writer(void *_count)
 	for (;;) {
 		new = test_array_alloc();
 		new->a = 8;
-		old = rcu_publish_content(&test_rcu_pointer, new);
+		old = rcu_xchg_pointer(&test_rcu_pointer, new);
+		synchronize_rcu();
 		/* can be done after unlock */
 		if (old)
 			old->a = 0;