X-Git-Url: https://git.lttng.org/?a=blobdiff_plain;f=markers-test%2Ftest-mark-speed.c;h=015ce4997f7c7cab9b52c014bdaa225dcc23dd3e;hb=31efe1f8304f09a4f4139c387a98d3215cd423c9;hp=bdaa56ce205583d0fc9dffa0162d28e809b4efaa;hpb=c78bfeb02b692f7eeb33dde77e7ff9bca5819191;p=lttv.git

diff --git a/markers-test/test-mark-speed.c b/markers-test/test-mark-speed.c
index bdaa56ce..015ce499 100644
--- a/markers-test/test-mark-speed.c
+++ b/markers-test/test-mark-speed.c
@@ -10,6 +10,28 @@
 #include <asm/ptrace.h>
 #include <asm/system.h>
 
+static void pmc_flush_cache(void)
+{
+    register int i;
+    /* write back and invalidate cache (a serializing instruction) */
+
+    __asm__ __volatile__ ( "wbinvd" : : : "memory" );
+
+    /* The wbinvd instruction does not wait for the external caches
+     * to be flushed, but only requests that it be done.  The loop
+     * is to be sure that enough time has elapsed, but the compiler
+     * might simplify or even remove it.  The loop bound is for a
+     * 512 KB L2 cache.  On a Pentium Pro/II/III, the loop uses
+     * 2 cycles per iteration.
+     *
+     * Does wbinvd also cause the TLB to be flushed?
+     * A comment in mtrr.c suggests that it does.
+     */
+    for (i = 0; i < 512*1024; i++) {
+    	cpu_relax();
+    }
+}
+
 static void noinline test2(const struct marker *mdata,
         void *call_private, ...)
 {
@@ -17,6 +39,12 @@ static void noinline test2(const struct marker *mdata,
 	printk("blah\n");
 }
 
+#ifdef CACHEFLUSH
+#define myclflush(a) clflush(a)
+#else
+#define myclflush(a)
+#endif									\
+
 /*
  * Generic marker flavor always available.
  * Note : the empty asm volatile with read constraint is used here instead of a
@@ -42,6 +70,7 @@ static void noinline test2(const struct marker *mdata,
 					(&__mark_##name, call_private,	\
 					## args);		\
 		} else {						\
+			myclflush(&_imv_read(__mark_##name.state));	\
 			if (unlikely(_imv_read(__mark_##name.state)))	\
 				test2			\
 					(&__mark_##name, call_private,	\
@@ -52,15 +81,9 @@ static void noinline test2(const struct marker *mdata,
 	//asm volatile ("");
 struct proc_dir_entry *pentry = NULL;
 
-char temp0[8192];
-int temp[8192];
-char temp5[8192];
-
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-#ifdef CACHEFLUSH
-	wbinvd();
-#endif
+	volatile int temp[5];
 	temp[2] = (temp[0] + 60) << 10;
 	temp[3] = (temp[2] + 60) << 10;
 	temp[4] = (temp[3] + 60) << 10;
@@ -80,8 +103,8 @@ static int my_open(struct inode *inode, struct file *file)
 
 	local_irq_save(flags);
 #ifdef CACHEFLUSH
-	wbinvd();	/* initial write back, without cycle count */
-	msleep(20);	/* wait for L2 flush */
+	//pmc_flush_cache();	/* initial write back, without cycle count */
+	//msleep(20);	/* wait for L2 flush */
 #endif
 	rdtsc_barrier();
 	cycles1 = get_cycles();