X-Git-Url: https://git.lttng.org/?a=blobdiff_plain;f=markers-test%2Ftest-mark-speed.c;h=015ce4997f7c7cab9b52c014bdaa225dcc23dd3e;hb=31efe1f8304f09a4f4139c387a98d3215cd423c9;hp=a4c2675bf0b283ba5bd5b888575915fb166e7764;hpb=ef8a59e11d2dc7bbde5c006caee5e07b6d85fa65;p=lttv.git diff --git a/markers-test/test-mark-speed.c b/markers-test/test-mark-speed.c index a4c2675b..015ce499 100644 --- a/markers-test/test-mark-speed.c +++ b/markers-test/test-mark-speed.c @@ -11,7 +11,8 @@ #include static void pmc_flush_cache(void) - { +{ + register int i; /* write back and invalidate cache (a serializing instruction) */ __asm__ __volatile__ ( "wbinvd" : : : "memory" ); @@ -26,8 +27,10 @@ static void pmc_flush_cache(void) * Does wbinvd also cause the TLB to be flushed? * A comment in mtrr.c suggests that it does. */ - { register int i; for (i = 0; i < 512*1024; i++) { } } - } + for (i = 0; i < 512*1024; i++) { + cpu_relax(); + } +} static void noinline test2(const struct marker *mdata, void *call_private, ...) @@ -36,6 +39,12 @@ static void noinline test2(const struct marker *mdata, printk("blah\n"); } +#ifdef CACHEFLUSH +#define myclflush(a) clflush(a) +#else +#define myclflush(a) +#endif \ + /* * Generic marker flavor always available. * Note : the empty asm volatile with read constraint is used here instead of a @@ -61,6 +70,7 @@ static void noinline test2(const struct marker *mdata, (&__mark_##name, call_private, \ ## args); \ } else { \ + myclflush(&_imv_read(__mark_##name.state)); \ if (unlikely(_imv_read(__mark_##name.state))) \ test2 \ (&__mark_##name, call_private, \ @@ -73,10 +83,7 @@ struct proc_dir_entry *pentry = NULL; static inline void test(unsigned long arg, unsigned long arg2) { - int temp[5]; -#ifdef CACHEFLUSH - pmc_flush_cache(); -#endif + volatile int temp[5]; temp[2] = (temp[0] + 60) << 10; temp[3] = (temp[2] + 60) << 10; temp[4] = (temp[3] + 60) << 10; @@ -96,8 +103,8 @@ static int my_open(struct inode *inode, struct file *file) local_irq_save(flags); #ifdef CACHEFLUSH - pmc_flush_cache(); /* initial write back, without cycle count */ - msleep(20); /* wait for L2 flush */ + //pmc_flush_cache(); /* initial write back, without cycle count */ + //msleep(20); /* wait for L2 flush */ #endif rdtsc_barrier(); cycles1 = get_cycles();