X-Git-Url: https://git.lttng.org/?a=blobdiff_plain;ds=sidebyside;f=tests%2Ftest_qsbr_gc.c;h=12430d0d30d6f33f010a533a4ceceb3a04ae6937;hb=94b343fd8d68512d78d8646c646c15a1b3f84186;hp=d32d1a04175159bc186aeb9f3fbf6f98e98a837a;hpb=ec4e58a3aba2084440012f8ccac3a31eb6101183;p=urcu.git diff --git a/tests/test_qsbr_gc.c b/tests/test_qsbr_gc.c index d32d1a0..12430d0 100644 --- a/tests/test_qsbr_gc.c +++ b/tests/test_qsbr_gc.c @@ -32,12 +32,10 @@ #include #include #include +#include #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - /* hardcoded number of CPUs */ #define NR_CPUS 16384