#include <asm/ptrace.h>
#include <asm/system.h>
+static void pmc_flush_cache(void)
+ {
+ register int i;
+ /* write back and invalidate cache (a serializing instruction) */
+
+ __asm__ __volatile__ ( "wbinvd" : : : "memory" );
+
+ /* The wbinvd instruction does not wait for the external caches
+ * to be flushed, but only requests that it be done. The loop
+ * is to be sure that enough time has elapsed, but the compiler
+ * might simplify or even remove it. The loop bound is for a
+ * 512 KB L2 cache. On a Pentium Pro/II/III, the loop uses
+ * 2 cycles per iteration.
+ *
+ * Does wbinvd also cause the TLB to be flushed?
+ * A comment in mtrr.c suggests that it does.
+ */
+
+ for (i = 0; i < 512*1024; i++) {
+ cpu_relax();
+ }
+ }
+
+
+
static void noinline test2(const struct marker *mdata,
void *call_private, ...)
{
//asm volatile ("");
struct proc_dir_entry *pentry = NULL;
-int temp __cacheline_aligned = 10;
-int temp2 __cacheline_aligned = 10;
-
static inline void test(unsigned long arg, unsigned long arg2)
{
+ volatile int temp[5];
#ifdef CACHEFLUSH
- wbinvd();
+ clflush(¤t->pid);
+ //pmc_flush_cache();
#endif
- temp = (temp + 60) << 10;
+ temp[2] = (temp[0] + 60) << 10;
+ temp[3] = (temp[2] + 60) << 10;
+ temp[4] = (temp[3] + 60) << 10;
+ temp[0] = (temp[4] + 60) << 10;
//asm volatile ("");
//__my_trace_mark(1, kernel_debug_test, NULL, "%d %d %ld %ld", 2, current->pid, arg, arg2);
barrier();
unsigned long flags;
local_irq_save(flags);
+#ifdef CACHEFLUSH
+ //pmc_flush_cache(); /* initial write back, without cycle count */
+ //msleep(20); /* wait for L2 flush */
+#endif
rdtsc_barrier();
cycles1 = get_cycles();
rdtsc_barrier();
cycles2 = get_cycles();
rdtsc_barrier();
local_irq_restore(flags);
- printk("cycles : %llu\n", (cycles2-cycles1)/20000);
+ printk("cycles : %llu\n", cycles2-cycles1);
return -EPERM;
}