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[lttv.git] / markers-test / test-mark-speed-edit.c

diff --git a/markers-test/test-mark-speed-edit.c b/markers-test/test-mark-speed-edit.c
index 2aeab6e2a9347ac80cc8f59dd28788ab9802dde9..dbb72faa4daf75d79ab21281b6112299355a3d60 100644 (file)
--- a/markers-test/test-mark-speed-edit.c
+++ b/markers-test/test-mark-speed-edit.c
@@ -12,6 +12,7 @@
 
 static void pmc_flush_cache(void)
   {
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,7 +27,10 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
+    
+     for (i = 0; i < 512*1024; i++) {
+       cpu_relax();
+     }
   }
 
 
@@ -85,9 +89,10 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-       register int temp[5];
+       volatile int temp[5];
 #ifdef CACHEFLUSH
-       pmc_flush_cache();
+       clflush(&current->pid);
+       //pmc_flush_cache();
 #endif
        temp[2] = (temp[0] + 60) << 10;
        temp[3] = (temp[2] + 60) << 10;
@@ -109,8 +114,8 @@ static int my_open(struct inode *inode, struct file *file)
 
        local_irq_save(flags);
 #ifdef CACHEFLUSH
-       pmc_flush_cache();      /* initial write back, without cycle count */
-       msleep(20);     /* wait for L2 flush */
+       //pmc_flush_cache();    /* initial write back, without cycle count */
+       //msleep(20);   /* wait for L2 flush */
 #endif
        rdtsc_barrier();
        cycles1 = get_cycles();