X-Git-Url: http://git.lttng.org/?a=blobdiff_plain;f=urcu%2Farch%2Fx86.h;h=a5b3a23b385f26f7aea6b5daaf70cab762fc4262;hb=67ecffc0f530a7b5c4dd5111ea7dd3213da8eb91;hp=5853604932793fb5fe40b5244fc5b33042393437;hpb=e51500edbd9919cee53bc85cbb4b22cd4786fc42;p=userspace-rcu.git diff --git a/urcu/arch/x86.h b/urcu/arch/x86.h index 5853604..a5b3a23 100644 --- a/urcu/arch/x86.h +++ b/urcu/arch/x86.h @@ -24,10 +24,11 @@ #include #include +#include #ifdef __cplusplus extern "C" { -#endif +#endif #define CAA_CACHE_LINE_SIZE 128 @@ -55,12 +56,20 @@ extern "C" { * IDT WinChip supports weak store ordering, and the kernel may enable it * under our feet; cmm_smp_wmb() ceases to be a nop for these processors. */ +#if (CAA_BITS_PER_LONG == 32) #define cmm_mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory") -#define cmm_rmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory") -#define cmm_wmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)"::: "memory") +#define cmm_rmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory") +#define cmm_wmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory") +#else +#define cmm_mb() __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory") +#define cmm_rmb() __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory") +#define cmm_wmb() __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory") +#endif #endif -#define caa_cpu_relax() __asm__ __volatile__ ("rep; nop" : : : "memory"); +#define caa_cpu_relax() __asm__ __volatile__ ("rep; nop" : : : "memory") + +#define HAS_CAA_GET_CYCLES #define rdtscll(val) \ do { \ @@ -80,7 +89,21 @@ static inline cycles_t caa_get_cycles(void) return ret; } -#ifdef __cplusplus +/* + * Define the membarrier system call number if not yet available in the + * system headers. + */ +#if (CAA_BITS_PER_LONG == 32) +#ifndef __NR_membarrier +#define __NR_membarrier 375 +#endif +#else +#ifndef __NR_membarrier +#define __NR_membarrier 324 +#endif +#endif + +#ifdef __cplusplus } #endif