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Update formal model from local copy
[urcu.git]
/
tests
/
test_qsbr_gc.c
diff --git
a/tests/test_qsbr_gc.c
b/tests/test_qsbr_gc.c
index d32d1a04175159bc186aeb9f3fbf6f98e98a837a..97660676e548f08d55cc7b3aadf51c066c03338d 100644
(file)
--- a/
tests/test_qsbr_gc.c
+++ b/
tests/test_qsbr_gc.c
@@
-35,9
+35,6
@@
#include <urcu/arch.h>
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
/* hardcoded number of CPUs */
#define NR_CPUS 16384
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