//asm volatile ("");
struct proc_dir_entry *pentry = NULL;
-int temp __cacheline_aligned = 10;
-int temp2 __cacheline_aligned = 10;
+char temp0[8192];
+int temp[8192] __cacheline_aligned;
+char temp5[8192];
static inline void test(unsigned long arg, unsigned long arg2)
{
#ifdef CACHEFLUSH
wbinvd();
#endif
- temp = (temp + 60) << 10;
+ temp[2] = (temp[0] + 60) << 10;
+ temp[3] = (temp[2] + 60) << 10;
+ temp[4] = (temp[3] + 60) << 10;
+ temp[0] = (temp[4] + 60) << 10;
//asm volatile ("");
barrier();
__my_trace_mark(1, kernel_debug_test, NULL, "%d %d %ld %ld", 2, current->pid, arg, arg2);
unsigned long flags;
local_irq_save(flags);
+#ifdef CACHEFLUSH
+ wbinvd(); /* initial write back, without cycle count */
+ msleep(20); /* wait for L2 flush */
+#endif
rdtsc_barrier();
cycles1 = get_cycles();
rdtsc_barrier();