#include <stddef.h>
#include <string.h>
+#include <urcu-bp.h>
extern __thread long ust_reg_stack[500];
extern volatile __thread long *ust_reg_stack_ptr;
-#ifndef __x86_64
+#define ____cacheline_aligned __attribute__((aligned(CAA_CACHE_LINE_SIZE)))
+
+#ifdef __i386
struct registers {
short ss;
long esp;
};
+static inline int fls(int x)
+{
+ int r;
+ asm("bsrl %1,%0\n\t"
+ "cmovzl %2,%0"
+ : "=&r" (r) : "rm" (x), "rm" (-1));
+ return r + 1;
+}
+
#ifdef CONFIG_UST_GDB_INTEGRATION
/* save_registers - saves most of the processor's registers so
#define RELATIVE_ADDRESS(__rel_label__) __rel_label__
-#define ARCH_COPY_ADDR(src, dst) "lea " src "," dst
+#define ARCH_COPY_ADDR(dst) "lea 2b," dst "\n\t"
#define _ASM_PTR ".long "
-#else /* below is code for x86-64 */
+#elif defined(__x86_64)
struct registers {
int padding; /* 4 bytes */
unsigned long rsp;
};
+static inline int fls(int x)
+{
+ int r;
+ asm("bsrl %1,%0\n\t"
+ "cmovzl %2,%0"
+ : "=&r" (r) : "rm" (x), "rm" (-1));
+ return r + 1;
+}
+
#ifdef CONFIG_UST_GDB_INTEGRATION
#define save_registers(regsptr) \
/* Start TLS access of private reg stack pointer */ \
".byte 0x66\n\t" \
"leaq ust_reg_stack_ptr@tlsgd(%%rip), %%rdi\n\t" \
- ".word 0x6666\n\t" \
+ ".hword 0x6666\n\t" \
"rex64\n\t" \
"call __tls_get_addr@plt\n\t" \
/* --- End TLS access */ \
/* Start TLS access of private reg stack */ \
".byte 0x66\n\t" \
"leaq ust_reg_stack@tlsgd(%%rip), %%rdi\n\t" \
- ".word 0x6666\n\t" \
+ ".hword 0x6666\n\t" \
"rex64\n\t" \
"call __tls_get_addr@plt\n\t" \
/* --- End TLS access */ \
* in a relocatable way. On x86-64, this uses a special (%rip) notation. */
#define RELATIVE_ADDRESS(__rel_label__) __rel_label__(%%rip)
-#define ARCH_COPY_ADDR(src, dst) "lea " src "(%%rip)," dst
+#define ARCH_COPY_ADDR(dst) "lea 2b(%%rip)," dst "\n\t"
#define _ASM_PTR ".quad "
+#elif defined(__PPC__)
+
+struct registers {
+};
+
+static __inline__ int fls(unsigned int x)
+{
+ int lz;
+
+ asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
+ return 32 - lz;
+}
+
+#define ARCH_COPY_ADDR(dst) \
+ "lis " dst ",2b@h\n\t" /* load high bytes */ \
+ "ori " dst "," dst ",2b@l\n\t" /* load low bytes */
+
+#define _ASM_PTR ".long "
+#define save_registers(a)
+
+#else /* arch-agnostic */
+
+static __inline__ int fls(unsigned int x)
+{
+ int r = 32;
+
+ if (!x)
+ return 0;
+ if (!(x & 0xFFFF0000U)) {
+ x <<= 16;
+ r -= 16;
+ }
+ if (!(x & 0xFF000000U)) {
+ x <<= 8;
+ r -= 8;
+ }
+ if (!(x & 0xF0000000U)) {
+ x <<= 4;
+ r -= 4;
+ }
+ if (!(x & 0xC0000000U)) {
+ x <<= 2;
+ r -= 2;
+ }
+ if (!(x & 0x80000000U)) {
+ x <<= 1;
+ r -= 1;
+ }
+ return r;
+}
+
#endif
+#ifdef __arm__
+
+struct registers {
+};
+
+#define ARCH_COPY_ADDR(dst) "ldr "dst", =2b\n\t" \
+ "b 55f\n\t" \
+ ".ltorg\n\t" \
+ "55:\n\t"
+
+#define _ASM_PTR ".long "
+#define save_registers(a)
+
+#endif /* __arm__ */
+
#endif /* UST_PROCESSOR_H */