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QSBR: Implement 2-phase grace period for 32-bit arch
[urcu.git]
/
arch_atomic_x86.h
diff --git
a/arch_atomic_x86.h
b/arch_atomic_x86.h
index e9a0b3e851e13a3d17f893573cd2de1d89772044..f471a393960d009587e2a6d0b0d8eb25f158683f 100644
(file)
--- a/
arch_atomic_x86.h
+++ b/
arch_atomic_x86.h
@@
-27,13
+27,10
@@
#ifndef _INCLUDE_API_H
/*
#ifndef _INCLUDE_API_H
/*
- * Using a isync as second barrier for exchange to provide acquire semantic.
- * According to atomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
- * explicit that this also has acquire semantics."
* Derived from AO_compare_and_swap() and AO_test_and_set_full().
*/
* Derived from AO_compare_and_swap() and AO_test_and_set_full().
*/
-static __attribute__((always_inline))
+static
inline
__attribute__((always_inline))
unsigned int atomic_exchange_32(volatile unsigned int *addr, unsigned int val)
{
unsigned int result;
unsigned int atomic_exchange_32(volatile unsigned int *addr, unsigned int val)
{
unsigned int result;
@@
-50,7
+47,7
@@
unsigned int atomic_exchange_32(volatile unsigned int *addr, unsigned int val)
#if (BITS_PER_LONG == 64)
#if (BITS_PER_LONG == 64)
-static __attribute__((always_inline))
+static
inline
__attribute__((always_inline))
unsigned long atomic_exchange_64(volatile unsigned long *addr,
unsigned long val)
{
unsigned long atomic_exchange_64(volatile unsigned long *addr,
unsigned long val)
{
@@
-68,7
+65,7
@@
unsigned long atomic_exchange_64(volatile unsigned long *addr,
#endif
#endif
-static __attribute__((always_inline))
+static
inline
__attribute__((always_inline))
unsigned long _atomic_exchange(volatile void *addr, unsigned long val, int len)
{
switch (len) {
unsigned long _atomic_exchange(volatile void *addr, unsigned long val, int len)
{
switch (len) {
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