1 // SPDX-FileCopyrightText: 2009 Paul E. McKenney, IBM Corporation.
2 // SPDX-FileCopyrightText: 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
4 // SPDX-License-Identifier: LGPL-2.1-or-later
6 #ifndef _URCU_ARCH_PPC_H
7 #define _URCU_ARCH_PPC_H
10 * arch_ppc.h: trivial definitions for the powerpc architecture.
13 #include <urcu/compiler.h>
14 #include <urcu/config.h>
15 #include <urcu/syscall-compat.h>
23 * Most powerpc machines have 128 bytes cache lines, but to make sure
24 * there is no false sharing on all known Power hardware, use the
25 * largest known cache line size, which is the physical size of POWER5
26 * L3 cache lines (256 bytes).
28 * "Each slice [of the L3] is 12-way set-associative, with 4,096
29 * congruence classes of 256-byte lines managed as two 128-byte sectors
30 * to match the L2 line size."
32 * From: "POWER5 system microarchitecture",
33 * IBM Journal of Research & Development,
34 * vol. 49, no. 4/5, July/September 2005
35 * https://www.eecg.utoronto.ca/~moshovos/ACA08/readings/power5.pdf
37 * This value is a compile-time constant, which prevents us from
38 * querying the processor for the cache line size at runtime. We
39 * therefore need to be pessimistic and assume the largest known cache
42 * This value is exposed through public headers, so tuning it for
43 * specific environments is a concern for ABI compatibility between
44 * applications and liburcu.
46 #define CAA_CACHE_LINE_SIZE 256
49 #define LWSYNC_OPCODE "sync\n"
51 #define LWSYNC_OPCODE "lwsync\n"
55 * Use sync for all cmm_mb/rmb/wmb barriers because lwsync does not
56 * preserve ordering of cacheable vs. non-cacheable accesses, so it
57 * should not be used to order with respect to MMIO operations. An
58 * eieio+lwsync pair is also not enough for cmm_rmb, because it will
59 * order cacheable and non-cacheable memory operations separately---i.e.
60 * not the latter against the former.
62 #define cmm_mb() __asm__ __volatile__ ("sync":::"memory")
65 * lwsync orders loads in cacheable memory with respect to other loads,
66 * and stores in cacheable memory with respect to other stores.
67 * Therefore, use it for barriers ordering accesses to cacheable memory
70 #define cmm_smp_rmb() __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
71 #define cmm_smp_wmb() __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
77 __asm__ __volatile__ ("mftb %0" : "=r" (rval)); \
85 __asm__ __volatile__ ("mftbu %0" : "=r" (rval)); \
92 unsigned long long rval; \
93 __asm__ __volatile__ ("mftb %0" : "=r" (rval)); \
97 #define HAS_CAA_GET_CYCLES
99 typedef uint64_t caa_cycles_t
;
102 static inline caa_cycles_t
caa_get_cycles(void)
104 return (caa_cycles_t
) mftb();
107 static inline caa_cycles_t
caa_get_cycles(void)
117 return (((caa_cycles_t
) h
) << 32) + l
;
123 * On Linux, define the membarrier system call number if not yet available in
124 * the system headers.
126 #if (defined(__linux__) && !defined(__NR_membarrier))
127 #define __NR_membarrier 365
134 #include <urcu/arch/generic.h>
136 #endif /* _URCU_ARCH_PPC_H */
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