2 // Poison value for freed memory
4 // Memory with correct data
8 #define read_poison (data_read_first[0] == POISON)
10 #define RCU_GP_CTR_BIT (1 << 7)
11 #define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
14 #define REMOTE_BARRIERS
18 //#define ARCH_POWERPC
20 * mem.spin: Promela code to validate memory barriers with OOO memory
21 * and out-of-order instruction scheduling.
23 * This program is free software; you can redistribute it and/or modify
24 * it under the terms of the GNU General Public License as published by
25 * the Free Software Foundation; either version 2 of the License, or
26 * (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
37 * Copyright (c) 2009 Mathieu Desnoyers
40 /* Promela validation variables. */
42 /* specific defines "included" here */
43 /* DEFINES file "included" here */
50 #define get_pid() (_pid)
52 #define get_readerid() (get_pid())
55 * Produced process control and data flow. Updated after each instruction to
56 * show which variables are ready. Using one-hot bit encoding per variable to
57 * save state space. Used as triggers to execute the instructions having those
58 * variables as input. Leaving bits active to inhibit instruction execution.
59 * Scheme used to make instruction disabling and automatic dependency fall-back
63 #define CONSUME_TOKENS(state, bits, notbits) \
64 ((!(state & (notbits))) && (state & (bits)) == (bits))
66 #define PRODUCE_TOKENS(state, bits) \
67 state = state | (bits);
69 #define CLEAR_TOKENS(state, bits) \
70 state = state & ~(bits)
73 * Types of dependency :
77 * - True dependency, Read-after-Write (RAW)
79 * This type of dependency happens when a statement depends on the result of a
80 * previous statement. This applies to any statement which needs to read a
81 * variable written by a preceding statement.
83 * - False dependency, Write-after-Read (WAR)
85 * Typically, variable renaming can ensure that this dependency goes away.
86 * However, if the statements must read and then write from/to the same variable
87 * in the OOO memory model, renaming may be impossible, and therefore this
88 * causes a WAR dependency.
90 * - Output dependency, Write-after-Write (WAW)
92 * Two writes to the same variable in subsequent statements. Variable renaming
93 * can ensure this is not needed, but can be required when writing multiple
94 * times to the same OOO mem model variable.
98 * Execution of a given instruction depends on a previous instruction evaluating
99 * in a way that allows its execution. E.g. : branches.
101 * Useful considerations for joining dependencies after branch
105 * "We say box i dominates box j if every path (leading from input to output
106 * through the diagram) which passes through box j must also pass through box
107 * i. Thus box i dominates box j if box j is subordinate to box i in the
110 * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
111 * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
115 * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
116 * output exchanged. Therefore, i post-dominating j ensures that every path
117 * passing by j will pass by i before reaching the output.
119 * Prefetch and speculative execution
121 * If an instruction depends on the result of a previous branch, but it does not
122 * have side-effects, it can be executed before the branch result is known.
123 * however, it must be restarted if a core-synchronizing instruction is issued.
124 * Note that instructions which depend on the speculative instruction result
125 * but that have side-effects must depend on the branch completion in addition
126 * to the speculatively executed instruction.
128 * Other considerations
130 * Note about "volatile" keyword dependency : The compiler will order volatile
131 * accesses so they appear in the right order on a given CPU. They can be
132 * reordered by the CPU instruction scheduling. This therefore cannot be
133 * considered as a depencency.
137 * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
138 * Kaufmann. ISBN 1-55860-698-X.
139 * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
140 * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
142 * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
143 * Morgan Kaufmann. ISBN 1-55860-320-4.
147 * Note about loops and nested calls
149 * To keep this model simple, loops expressed in the framework will behave as if
150 * there was a core synchronizing instruction between loops. To see the effect
151 * of loop unrolling, manually unrolling loops is required. Note that if loops
152 * end or start with a core synchronizing instruction, the model is appropriate.
153 * Nested calls are not supported.
157 * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
158 * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
159 * http://www.linuxjournal.com/article/8212)
162 #define HAVE_OOO_CACHE_READ
166 * Each process have its own data in cache. Caches are randomly updated.
167 * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
171 typedef per_proc_byte {
175 typedef per_proc_bit {
179 /* Bitfield has a maximum of 8 procs */
180 typedef per_proc_bitfield {
184 #define DECLARE_CACHED_VAR(type, x) \
187 #define DECLARE_PROC_CACHED_VAR(type, x)\
191 #define INIT_CACHED_VAR(x, v) \
194 #define INIT_PROC_CACHED_VAR(x, v) \
195 cache_dirty_##x = 0; \
198 #define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
200 #define READ_CACHED_VAR(x) (cached_##x)
202 #define WRITE_CACHED_VAR(x, v) \
205 cache_dirty_##x = 1; \
208 #define CACHE_WRITE_TO_MEM(x, id) \
210 :: IS_CACHE_DIRTY(x, id) -> \
211 mem_##x = cached_##x; \
212 cache_dirty_##x = 0; \
217 #define CACHE_READ_FROM_MEM(x, id) \
219 :: !IS_CACHE_DIRTY(x, id) -> \
220 cached_##x = mem_##x; \
226 * May update other caches if cache is dirty, or not.
228 #define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
230 :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
234 #define RANDOM_CACHE_READ_FROM_MEM(x, id)\
236 :: 1 -> CACHE_READ_FROM_MEM(x, id); \
240 /* Must consume all prior read tokens. All subsequent reads depend on it. */
244 CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
248 CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
250 :: i >= NR_READERS -> break
252 CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
256 CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
258 :: i >= SLAB_SIZE -> break
263 /* Must consume all prior write tokens. All subsequent writes depend on it. */
267 CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
271 CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
273 :: i >= NR_READERS -> break
275 CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
279 CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
281 :: i >= SLAB_SIZE -> break
286 /* Synchronization point. Must consume all prior read and write tokens. All
287 * subsequent reads and writes depend on it. */
296 #ifdef REMOTE_BARRIERS
298 bit reader_barrier[NR_READERS];
301 * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
302 * because they would add unexisting core synchronization and would therefore
303 * create an incomplete model.
304 * Therefore, we model the read-side memory barriers by completely disabling the
305 * memory barriers and their dependencies from the read-side. One at a time
306 * (different verification runs), we make a different instruction listen for
310 #define smp_mb_reader(i, j)
313 * Service 0, 1 or many barrier requests.
315 inline smp_mb_recv(i, j)
318 :: (reader_barrier[get_readerid()] == 1) ->
320 * We choose to ignore cycles caused by writer busy-looping,
321 * waiting for the reader, sending barrier requests, and the
322 * reader always services them without continuing execution.
324 progress_ignoring_mb1:
326 reader_barrier[get_readerid()] = 0;
329 * We choose to ignore writer's non-progress caused by the
330 * reader ignoring the writer's mb() requests.
332 progress_ignoring_mb2:
337 #define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
339 #define smp_mb_send(i, j, progressid) \
344 :: i < NR_READERS -> \
345 reader_barrier[i] = 1; \
347 * Busy-looping waiting for reader barrier handling is of little\
348 * interest, given the reader has the ability to totally ignore \
349 * barrier requests. \
352 :: (reader_barrier[i] == 1) -> \
353 PROGRESS_LABEL(progressid) \
355 :: (reader_barrier[i] == 0) -> break; \
358 :: i >= NR_READERS -> \
366 #define smp_mb_send(i, j, progressid) smp_mb(i)
367 #define smp_mb_reader(i, j) smp_mb(i)
368 #define smp_mb_recv(i, j)
372 /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
373 DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
374 /* Note ! currently only one reader */
375 DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
377 DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
381 DECLARE_CACHED_VAR(bit, rcu_ptr);
382 bit ptr_read_first[NR_READERS];
384 DECLARE_CACHED_VAR(byte, rcu_ptr);
385 byte ptr_read_first[NR_READERS];
388 bit data_read_first[NR_READERS];
392 inline wait_init_done()
395 :: init_done == 0 -> skip;
403 RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
407 RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
410 :: i >= NR_READERS -> break
412 RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
416 RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
418 :: i >= SLAB_SIZE -> break
420 #ifdef HAVE_OOO_CACHE_READ
421 RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
425 RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
428 :: i >= NR_READERS -> break
430 RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
434 RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
436 :: i >= SLAB_SIZE -> break
440 #endif /* HAVE_OOO_CACHE_READ */
445 * Bit encoding, urcu_reader :
448 int _proc_urcu_reader;
449 #define proc_urcu_reader _proc_urcu_reader
451 /* Body of PROCEDURE_READ_LOCK */
452 #define READ_PROD_A_READ (1 << 0)
453 #define READ_PROD_B_IF_TRUE (1 << 1)
454 #define READ_PROD_B_IF_FALSE (1 << 2)
455 #define READ_PROD_C_IF_TRUE_READ (1 << 3)
457 #define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
458 :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
460 tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
461 PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
462 :: CONSUME_TOKENS(proc_urcu_reader, \
463 READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
464 (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
466 :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
467 PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
469 PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
472 :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
473 READ_PROD_C_IF_TRUE_READ << base) -> \
475 tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
476 PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
477 :: CONSUME_TOKENS(proc_urcu_reader, \
478 (READ_PROD_B_IF_TRUE \
479 | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
480 | READ_PROD_A_READ) << base, /* WAR */ \
483 WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
484 PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
485 /* IF_MERGE implies \
486 * post-dominance */ \
488 :: CONSUME_TOKENS(proc_urcu_reader, \
489 (READ_PROD_B_IF_FALSE /* pre-dominant */ \
490 | READ_PROD_A_READ) << base, /* WAR */ \
493 WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
495 PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
496 /* IF_MERGE implies \
497 * post-dominance */ \
501 /* Body of PROCEDURE_READ_LOCK */
502 #define READ_PROC_READ_UNLOCK (1 << 0)
504 #define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
505 :: CONSUME_TOKENS(proc_urcu_reader, \
507 READ_PROC_READ_UNLOCK << base) -> \
509 tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
510 PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
511 :: CONSUME_TOKENS(proc_urcu_reader, \
513 | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
516 WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
517 PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
521 #define READ_PROD_NONE (1 << 0)
523 /* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
524 #define READ_LOCK_BASE 1
525 #define READ_LOCK_OUT (1 << 5)
527 #define READ_PROC_FIRST_MB (1 << 6)
529 #define READ_PROC_READ_GEN (1 << 12)
530 #define READ_PROC_ACCESS_GEN (1 << 13)
532 #define READ_PROC_SECOND_MB (1 << 16)
534 /* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
535 #define READ_UNLOCK_BASE 17
536 #define READ_UNLOCK_OUT (1 << 18)
538 /* Should not include branches */
539 #define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
541 | READ_PROC_FIRST_MB \
542 | READ_PROC_READ_GEN \
543 | READ_PROC_ACCESS_GEN \
544 | READ_PROC_SECOND_MB \
547 /* Must clear all tokens, including branches */
548 #define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
550 inline urcu_one_read(i, j, nest_i, tmp, tmp2)
552 PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
555 PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
556 PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
559 #ifdef REMOTE_BARRIERS
560 PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
561 PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
567 #ifdef REMOTE_BARRIERS
569 * Signal-based memory barrier will only execute when the
570 * execution order appears in program order.
576 :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
578 | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
580 || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
582 READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
584 || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
586 | READ_PROC_READ_GEN, READ_PROC_ACCESS_GEN
588 || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
590 | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
592 || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
594 | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
595 | READ_UNLOCK_OUT, 0) ->
603 goto non_atomic3_skip;
606 goto non_atomic3_end;
609 #endif /* REMOTE_BARRIERS */
613 PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
615 :: CONSUME_TOKENS(proc_urcu_reader,
616 READ_LOCK_OUT, /* post-dominant */
617 READ_PROC_FIRST_MB) ->
619 PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
621 :: CONSUME_TOKENS(proc_urcu_reader,
622 READ_PROC_FIRST_MB, /* mb() orders reads */
623 READ_PROC_READ_GEN) ->
625 ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
626 PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
628 :: CONSUME_TOKENS(proc_urcu_reader,
629 READ_PROC_FIRST_MB /* mb() orders reads */
630 | READ_PROC_READ_GEN,
631 READ_PROC_ACCESS_GEN) ->
632 /* smp_read_barrier_depends */
635 data_read_first[get_readerid()] =
636 READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
637 PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
640 :: CONSUME_TOKENS(proc_urcu_reader,
641 READ_PROC_ACCESS_GEN /* mb() orders reads */
642 | READ_PROC_READ_GEN /* mb() orders reads */
643 | READ_PROC_FIRST_MB /* mb() ordered */
644 | READ_LOCK_OUT, /* post-dominant */
645 READ_PROC_SECOND_MB) ->
647 PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
649 PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
650 READ_PROC_SECOND_MB /* mb() orders reads */
651 | READ_PROC_FIRST_MB /* mb() orders reads */
652 | READ_LOCK_OUT, /* RAW */
655 :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
656 CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
662 * Dependency between consecutive loops :
664 * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
665 * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
667 * _WHEN THE MB()s are in place_, they add full ordering of the
668 * generation pointer read wrt active reader count read, which ensures
669 * execution will not spill across loop execution.
670 * However, in the event mb()s are removed (execution using signal
671 * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
672 * to spill its execution on other loop's execution.
688 active proctype urcu_reader()
693 /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
694 DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
695 /* Note ! currently only one reader */
696 DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
698 DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
702 DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
704 DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
708 INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
709 INIT_PROC_CACHED_VAR(rcu_ptr, 0);
714 INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
716 :: i >= NR_READERS -> break
718 INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
722 INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
724 :: i >= SLAB_SIZE -> break
730 assert(get_pid() < NR_PROCS);
736 * We do not test reader's progress here, because we are mainly
737 * interested in writer's progress. The reader never blocks
738 * anyway. We have to test for reader/writer's progress
739 * separately, otherwise we could think the writer is doing
740 * progress when it's blocked by an always progressing reader.
742 #ifdef READER_PROGRESS
745 urcu_one_read(i, j, nest_i, tmp, tmp2);
749 /* no name clash please */
750 #undef proc_urcu_reader
753 /* Model the RCU update process. */
756 * Bit encoding, urcu_writer :
757 * Currently only supports one reader.
760 int _proc_urcu_writer;
761 #define proc_urcu_writer _proc_urcu_writer
763 #define WRITE_PROD_NONE (1 << 0)
765 #define WRITE_DATA (1 << 1)
766 #define WRITE_PROC_WMB (1 << 2)
767 #define WRITE_XCHG_PTR (1 << 3)
769 #define WRITE_PROC_FIRST_MB (1 << 4)
772 #define WRITE_PROC_FIRST_READ_GP (1 << 5)
773 #define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
774 #define WRITE_PROC_FIRST_WAIT (1 << 7)
775 #define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
778 #define WRITE_PROC_SECOND_READ_GP (1 << 9)
779 #define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
780 #define WRITE_PROC_SECOND_WAIT (1 << 11)
781 #define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
783 #define WRITE_PROC_SECOND_MB (1 << 13)
785 #define WRITE_FREE (1 << 14)
787 #define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
791 | WRITE_PROC_FIRST_MB \
792 | WRITE_PROC_FIRST_READ_GP \
793 | WRITE_PROC_FIRST_WRITE_GP \
794 | WRITE_PROC_FIRST_WAIT \
795 | WRITE_PROC_SECOND_READ_GP \
796 | WRITE_PROC_SECOND_WRITE_GP \
797 | WRITE_PROC_SECOND_WAIT \
798 | WRITE_PROC_SECOND_MB \
801 #define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
804 * Mutexes are implied around writer execution. A single writer at a time.
806 active proctype urcu_writer()
809 byte tmp, tmp2, tmpa;
810 byte cur_data = 0, old_data, loop_nr = 0;
811 byte cur_gp_val = 0; /*
812 * Keep a local trace of the current parity so
813 * we don't add non-existing dependencies on the global
814 * GP update. Needed to test single flip case.
817 /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
818 DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
819 /* Note ! currently only one reader */
820 DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
822 DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
826 DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
828 DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
832 INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
833 INIT_PROC_CACHED_VAR(rcu_ptr, 0);
838 INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
840 :: i >= NR_READERS -> break
842 INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
846 INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
848 :: i >= SLAB_SIZE -> break
855 assert(get_pid() < NR_PROCS);
859 #ifdef WRITER_PROGRESS
862 loop_nr = loop_nr + 1;
864 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
867 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
871 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
872 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
876 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
877 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
878 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
879 /* For single flip, we need to know the current parity */
880 cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
887 :: CONSUME_TOKENS(proc_urcu_writer,
891 cur_data = (cur_data + 1) % SLAB_SIZE;
892 WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
893 PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
896 :: CONSUME_TOKENS(proc_urcu_writer,
900 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
902 :: CONSUME_TOKENS(proc_urcu_writer,
905 /* rcu_xchg_pointer() */
907 old_data = READ_CACHED_VAR(rcu_ptr);
908 WRITE_CACHED_VAR(rcu_ptr, cur_data);
910 PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
912 :: CONSUME_TOKENS(proc_urcu_writer,
913 WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
914 WRITE_PROC_FIRST_MB) ->
917 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
920 :: CONSUME_TOKENS(proc_urcu_writer,
922 WRITE_PROC_FIRST_READ_GP) ->
923 tmpa = READ_CACHED_VAR(urcu_gp_ctr);
924 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
925 :: CONSUME_TOKENS(proc_urcu_writer,
926 WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
927 | WRITE_PROC_FIRST_READ_GP,
928 WRITE_PROC_FIRST_WRITE_GP) ->
930 WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
931 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
933 :: CONSUME_TOKENS(proc_urcu_writer,
934 //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
935 WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
936 WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
938 //smp_mb(i); /* TEST */
939 /* ONLY WAITING FOR READER 0 */
940 tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
942 /* In normal execution, we are always starting by
943 * waiting for the even parity.
945 cur_gp_val = RCU_GP_CTR_BIT;
948 :: (tmp2 & RCU_GP_CTR_NEST_MASK)
949 && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
950 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
952 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
955 :: CONSUME_TOKENS(proc_urcu_writer,
956 //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
957 WRITE_PROC_FIRST_WRITE_GP
958 | WRITE_PROC_FIRST_READ_GP
959 | WRITE_PROC_FIRST_WAIT_LOOP
960 | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
961 | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
963 #ifndef GEN_ERROR_WRITER_PROGRESS
966 /* The memory barrier will invalidate the
967 * second read done as prefetching. Note that all
968 * instructions with side-effects depending on
969 * WRITE_PROC_SECOND_READ_GP should also depend on
970 * completion of this busy-waiting loop. */
971 CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
975 /* This instruction loops to WRITE_PROC_FIRST_WAIT */
976 CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
979 :: CONSUME_TOKENS(proc_urcu_writer,
980 //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
981 WRITE_PROC_FIRST_WRITE_GP
982 | WRITE_PROC_FIRST_READ_GP
983 | WRITE_PROC_FIRST_MB,
984 WRITE_PROC_SECOND_READ_GP) ->
986 //smp_mb(i); /* TEST */
987 tmpa = READ_CACHED_VAR(urcu_gp_ctr);
988 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
989 :: CONSUME_TOKENS(proc_urcu_writer,
990 WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
991 * instruction has globally observable
994 | WRITE_PROC_FIRST_MB
996 | WRITE_PROC_FIRST_READ_GP
997 | WRITE_PROC_FIRST_WRITE_GP
998 | WRITE_PROC_SECOND_READ_GP,
999 WRITE_PROC_SECOND_WRITE_GP) ->
1001 WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
1002 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
1004 :: CONSUME_TOKENS(proc_urcu_writer,
1005 //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
1006 WRITE_PROC_FIRST_WAIT
1007 | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
1008 WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
1010 //smp_mb(i); /* TEST */
1011 /* ONLY WAITING FOR READER 0 */
1012 tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
1014 :: (tmp2 & RCU_GP_CTR_NEST_MASK)
1015 && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
1016 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
1018 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
1021 :: CONSUME_TOKENS(proc_urcu_writer,
1022 //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
1023 WRITE_PROC_SECOND_WRITE_GP
1024 | WRITE_PROC_FIRST_WRITE_GP
1025 | WRITE_PROC_SECOND_READ_GP
1026 | WRITE_PROC_FIRST_READ_GP
1027 | WRITE_PROC_SECOND_WAIT_LOOP
1028 | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
1029 | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
1031 #ifndef GEN_ERROR_WRITER_PROGRESS
1037 /* This instruction loops to WRITE_PROC_SECOND_WAIT */
1038 CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
1041 :: CONSUME_TOKENS(proc_urcu_writer,
1042 WRITE_PROC_FIRST_WAIT
1043 | WRITE_PROC_SECOND_WAIT
1044 | WRITE_PROC_FIRST_READ_GP
1045 | WRITE_PROC_SECOND_READ_GP
1046 | WRITE_PROC_FIRST_WRITE_GP
1047 | WRITE_PROC_SECOND_WRITE_GP
1048 | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
1049 | WRITE_PROC_FIRST_MB,
1050 WRITE_PROC_SECOND_MB) ->
1053 PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
1055 :: CONSUME_TOKENS(proc_urcu_writer,
1057 | WRITE_PROC_FIRST_WAIT
1058 | WRITE_PROC_SECOND_WAIT
1059 | WRITE_PROC_WMB /* No dependency on
1060 * WRITE_DATA because we
1062 * different location. */
1063 | WRITE_PROC_SECOND_MB
1064 | WRITE_PROC_FIRST_MB,
1066 WRITE_CACHED_VAR(rcu_data[old_data], POISON);
1067 PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
1069 :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
1070 CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
1076 * Note : Promela model adds implicit serialization of the
1077 * WRITE_FREE instruction. Normally, it would be permitted to
1078 * spill on the next loop execution. Given the validation we do
1079 * checks for the data entry read to be poisoned, it's ok if
1080 * we do not check "late arriving" memory poisoning.
1085 * Given the reader loops infinitely, let the writer also busy-loop
1086 * with progress here so, with weak fairness, we can test the
1087 * writer's progress.
1092 #ifdef WRITER_PROGRESS
1095 #ifdef READER_PROGRESS
1097 * Make sure we don't block the reader's progress.
1099 smp_mb_send(i, j, 5);
1104 /* Non-atomic parts of the loop */
1107 smp_mb_send(i, j, 1);
1108 goto smp_mb_send1_end;
1109 #ifndef GEN_ERROR_WRITER_PROGRESS
1111 smp_mb_send(i, j, 2);
1112 goto smp_mb_send2_end;
1114 smp_mb_send(i, j, 3);
1115 goto smp_mb_send3_end;
1118 smp_mb_send(i, j, 4);
1119 goto smp_mb_send4_end;
1124 /* no name clash please */
1125 #undef proc_urcu_writer
1128 /* Leave after the readers and writers so the pid count is ok. */
1133 INIT_CACHED_VAR(urcu_gp_ctr, 1);
1134 INIT_CACHED_VAR(rcu_ptr, 0);
1138 :: i < NR_READERS ->
1139 INIT_CACHED_VAR(urcu_active_readers[i], 0);
1140 ptr_read_first[i] = 1;
1141 data_read_first[i] = WINE;
1143 :: i >= NR_READERS -> break
1145 INIT_CACHED_VAR(rcu_data[0], WINE);
1149 INIT_CACHED_VAR(rcu_data[i], POISON);
1151 :: i >= SLAB_SIZE -> break