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[lttng-ust.git] / liblttng-ust / perf_event.h
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77d7fa98 1/*
c0c0989a
MJ		 2 * SPDX-License-Identifier: GPL-2.0-only
3 *
77d7fa98
MD		 4 * Performance events:
5 *
6 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
7 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
8 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
9 *
10 * Data type definitions, declarations, prototypes.
11 *
12 * Started by: Thomas Gleixner and Ingo Molnar
13 *
14 * Header copied from Linux kernel v4.7 installed headers.
77d7fa98 15 */
c0c0989a 16
77d7fa98
MD		 17#ifndef _UAPI_LINUX_PERF_EVENT_H
18#define _UAPI_LINUX_PERF_EVENT_H
19
20#include <linux/types.h>
21#include <linux/ioctl.h>
22#include <asm/byteorder.h>
23
24/*
25 * User-space ABI bits:
26 */
27
28/*
29 * attr.type
30 */
31enum perf_type_id {
32 PERF_TYPE_HARDWARE = 0,
33 PERF_TYPE_SOFTWARE = 1,
34 PERF_TYPE_TRACEPOINT = 2,
35 PERF_TYPE_HW_CACHE = 3,
36 PERF_TYPE_RAW = 4,
37 PERF_TYPE_BREAKPOINT = 5,
38
39 PERF_TYPE_MAX, /* non-ABI */
40};
41
42/*
43 * Generalized performance event event_id types, used by the
44 * attr.event_id parameter of the sys_perf_event_open()
45 * syscall:
46 */
47enum perf_hw_id {
48 /*
49 * Common hardware events, generalized by the kernel:
50 */
51 PERF_COUNT_HW_CPU_CYCLES = 0,
52 PERF_COUNT_HW_INSTRUCTIONS = 1,
53 PERF_COUNT_HW_CACHE_REFERENCES = 2,
54 PERF_COUNT_HW_CACHE_MISSES = 3,
55 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
56 PERF_COUNT_HW_BRANCH_MISSES = 5,
57 PERF_COUNT_HW_BUS_CYCLES = 6,
58 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,
59 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,
60 PERF_COUNT_HW_REF_CPU_CYCLES = 9,
61
62 PERF_COUNT_HW_MAX, /* non-ABI */
63};
64
65/*
66 * Generalized hardware cache events:
67 *
68 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
69 * { read, write, prefetch } x
70 * { accesses, misses }
71 */
72enum perf_hw_cache_id {
73 PERF_COUNT_HW_CACHE_L1D = 0,
74 PERF_COUNT_HW_CACHE_L1I = 1,
75 PERF_COUNT_HW_CACHE_LL = 2,
76 PERF_COUNT_HW_CACHE_DTLB = 3,
77 PERF_COUNT_HW_CACHE_ITLB = 4,
78 PERF_COUNT_HW_CACHE_BPU = 5,
79 PERF_COUNT_HW_CACHE_NODE = 6,
80
81 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
82};
83
84enum perf_hw_cache_op_id {
85 PERF_COUNT_HW_CACHE_OP_READ = 0,
86 PERF_COUNT_HW_CACHE_OP_WRITE = 1,
87 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
88
89 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */
90};
91
92enum perf_hw_cache_op_result_id {
93 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
94 PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
95
96 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */
97};
98
99/*
100 * Special "software" events provided by the kernel, even if the hardware
101 * does not support performance events. These events measure various
102 * physical and sw events of the kernel (and allow the profiling of them as
103 * well):
104 */
105enum perf_sw_ids {
106 PERF_COUNT_SW_CPU_CLOCK = 0,
107 PERF_COUNT_SW_TASK_CLOCK = 1,
108 PERF_COUNT_SW_PAGE_FAULTS = 2,
109 PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
110 PERF_COUNT_SW_CPU_MIGRATIONS = 4,
111 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
112 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
113 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
114 PERF_COUNT_SW_EMULATION_FAULTS = 8,
115 PERF_COUNT_SW_DUMMY = 9,
116 PERF_COUNT_SW_BPF_OUTPUT = 10,
117
118 PERF_COUNT_SW_MAX, /* non-ABI */
119};
120
121/*
122 * Bits that can be set in attr.sample_type to request information
123 * in the overflow packets.
124 */
125enum perf_event_sample_format {
126 PERF_SAMPLE_IP = 1U << 0,
127 PERF_SAMPLE_TID = 1U << 1,
128 PERF_SAMPLE_TIME = 1U << 2,
129 PERF_SAMPLE_ADDR = 1U << 3,
130 PERF_SAMPLE_READ = 1U << 4,
131 PERF_SAMPLE_CALLCHAIN = 1U << 5,
132 PERF_SAMPLE_ID = 1U << 6,
133 PERF_SAMPLE_CPU = 1U << 7,
134 PERF_SAMPLE_PERIOD = 1U << 8,
135 PERF_SAMPLE_STREAM_ID = 1U << 9,
136 PERF_SAMPLE_RAW = 1U << 10,
137 PERF_SAMPLE_BRANCH_STACK = 1U << 11,
138 PERF_SAMPLE_REGS_USER = 1U << 12,
139 PERF_SAMPLE_STACK_USER = 1U << 13,
140 PERF_SAMPLE_WEIGHT = 1U << 14,
141 PERF_SAMPLE_DATA_SRC = 1U << 15,
142 PERF_SAMPLE_IDENTIFIER = 1U << 16,
143 PERF_SAMPLE_TRANSACTION = 1U << 17,
144 PERF_SAMPLE_REGS_INTR = 1U << 18,
145
146 PERF_SAMPLE_MAX = 1U << 19, /* non-ABI */
147};
148
149/*
150 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
151 *
152 * If the user does not pass priv level information via branch_sample_type,
153 * the kernel uses the event's priv level. Branch and event priv levels do
154 * not have to match. Branch priv level is checked for permissions.
155 *
156 * The branch types can be combined, however BRANCH_ANY covers all types
157 * of branches and therefore it supersedes all the other types.
158 */
159enum perf_branch_sample_type_shift {
160 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */
161 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */
162 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */
163
164 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */
165 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */
166 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */
167 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */
168 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */
169 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */
170 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */
171 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */
172
173 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */
174 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */
175 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */
176
177 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */
178 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */
179
180 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */
181};
182
183enum perf_branch_sample_type {
184 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
185 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
186 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
187
188 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
189 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
190 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
191 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
192 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
193 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
194 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
195 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
196
197 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
198 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
199 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
200
201 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
202 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
203
204 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
205};
206
207#define PERF_SAMPLE_BRANCH_PLM_ALL \
208 (PERF_SAMPLE_BRANCH_USER|\
209 PERF_SAMPLE_BRANCH_KERNEL|\
210 PERF_SAMPLE_BRANCH_HV)
211
212/*
213 * Values to determine ABI of the registers dump.
214 */
215enum perf_sample_regs_abi {
216 PERF_SAMPLE_REGS_ABI_NONE = 0,
217 PERF_SAMPLE_REGS_ABI_32 = 1,
218 PERF_SAMPLE_REGS_ABI_64 = 2,
219};
220
221/*
222 * Values for the memory transaction event qualifier, mostly for
223 * abort events. Multiple bits can be set.
224 */
225enum {
226 PERF_TXN_ELISION = (1 << 0), /* From elision */
227 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */
228 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */
229 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */
230 PERF_TXN_RETRY = (1 << 4), /* Retry possible */
231 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */
232 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */
233 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */
234
235 PERF_TXN_MAX = (1 << 8), /* non-ABI */
236
237 /* bits 32..63 are reserved for the abort code */
238
239 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
240 PERF_TXN_ABORT_SHIFT = 32,
241};
242
243/*
244 * The format of the data returned by read() on a perf event fd,
245 * as specified by attr.read_format:
246 *
247 * struct read_format {
248 * { u64 value;
249 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
250 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
251 * { u64 id; } && PERF_FORMAT_ID
252 * } && !PERF_FORMAT_GROUP
253 *
254 * { u64 nr;
255 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
256 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
257 * { u64 value;
258 * { u64 id; } && PERF_FORMAT_ID
259 * } cntr[nr];
260 * } && PERF_FORMAT_GROUP
261 * };
262 */
263enum perf_event_read_format {
264 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0,
265 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1,
266 PERF_FORMAT_ID = 1U << 2,
267 PERF_FORMAT_GROUP = 1U << 3,
268
269 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */
270};
271
272#define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */
273#define PERF_ATTR_SIZE_VER1 72 /* add: config2 */
274#define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */
275#define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */
276 /* add: sample_stack_user */
277#define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */
278#define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */
279
280/*
281 * Hardware event_id to monitor via a performance monitoring event:
282 */
283struct perf_event_attr {
284
285 /*
286 * Major type: hardware/software/tracepoint/etc.
287 */
288 __u32 type;
289
290 /*
291 * Size of the attr structure, for fwd/bwd compat.
292 */
293 __u32 size;
294
295 /*
296 * Type specific configuration information.
297 */
298 __u64 config;
299
300 union {
301 __u64 sample_period;
302 __u64 sample_freq;
303 };
304
305 __u64 sample_type;
306 __u64 read_format;
307
308 __u64 disabled : 1, /* off by default */
309 inherit : 1, /* children inherit it */
310 pinned : 1, /* must always be on PMU */
311 exclusive : 1, /* only group on PMU */
312 exclude_user : 1, /* don't count user */
313 exclude_kernel : 1, /* ditto kernel */
314 exclude_hv : 1, /* ditto hypervisor */
315 exclude_idle : 1, /* don't count when idle */
316 mmap : 1, /* include mmap data */
317 comm : 1, /* include comm data */
318 freq : 1, /* use freq, not period */
319 inherit_stat : 1, /* per task counts */
320 enable_on_exec : 1, /* next exec enables */
321 task : 1, /* trace fork/exit */
322 watermark : 1, /* wakeup_watermark */
323 /*
324 * precise_ip:
325 *
326 * 0 - SAMPLE_IP can have arbitrary skid
327 * 1 - SAMPLE_IP must have constant skid
328 * 2 - SAMPLE_IP requested to have 0 skid
329 * 3 - SAMPLE_IP must have 0 skid
330 *
331 * See also PERF_RECORD_MISC_EXACT_IP
332 */
333 precise_ip : 2, /* skid constraint */
334 mmap_data : 1, /* non-exec mmap data */
335 sample_id_all : 1, /* sample_type all events */
336
337 exclude_host : 1, /* don't count in host */
338 exclude_guest : 1, /* don't count in guest */
339
340 exclude_callchain_kernel : 1, /* exclude kernel callchains */
341 exclude_callchain_user : 1, /* exclude user callchains */
342 mmap2 : 1, /* include mmap with inode data */
343 comm_exec : 1, /* flag comm events that are due to an exec */
344 use_clockid : 1, /* use @clockid for time fields */
345 context_switch : 1, /* context switch data */
346 write_backward : 1, /* Write ring buffer from end to beginning */
347 __reserved_1 : 36;
348
349 union {
350 __u32 wakeup_events; /* wakeup every n events */
351 __u32 wakeup_watermark; /* bytes before wakeup */
352 };
353
354 __u32 bp_type;
355 union {
356 __u64 bp_addr;
357 __u64 config1; /* extension of config */
358 };
359 union {
360 __u64 bp_len;
361 __u64 config2; /* extension of config1 */
362 };
363 __u64 branch_sample_type; /* enum perf_branch_sample_type */
364
365 /*
366 * Defines set of user regs to dump on samples.
367 * See asm/perf_regs.h for details.
368 */
369 __u64 sample_regs_user;
370
371 /*
372 * Defines size of the user stack to dump on samples.
373 */
374 __u32 sample_stack_user;
375
376 __s32 clockid;
377 /*
378 * Defines set of regs to dump for each sample
379 * state captured on:
380 * - precise = 0: PMU interrupt
381 * - precise > 0: sampled instruction
382 *
383 * See asm/perf_regs.h for details.
384 */
385 __u64 sample_regs_intr;
386
387 /*
388 * Wakeup watermark for AUX area
389 */
390 __u32 aux_watermark;
391 __u32 __reserved_2; /* align to __u64 */
392};
393
394#define perf_flags(attr) (*(&(attr)->read_format + 1))
395
396/*
397 * Ioctls that can be done on a perf event fd:
398 */
399#define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
400#define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
401#define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
402#define PERF_EVENT_IOC_RESET _IO ('$', 3)
403#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
404#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
405#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
406#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
407#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32)
408#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32)
409
410enum perf_event_ioc_flags {
411 PERF_IOC_FLAG_GROUP = 1U << 0,
412};
413
414/*
415 * Structure of the page that can be mapped via mmap
416 */
417struct perf_event_mmap_page {
418 __u32 version; /* version number of this structure */
419 __u32 compat_version; /* lowest version this is compat with */
420
421 /*
422 * Bits needed to read the hw events in user-space.
423 *
424 * u32 seq, time_mult, time_shift, index, width;
425 * u64 count, enabled, running;
426 * u64 cyc, time_offset;
427 * s64 pmc = 0;
428 *
429 * do {
430 * seq = pc->lock;
431 * barrier()
432 *
433 * enabled = pc->time_enabled;
434 * running = pc->time_running;
435 *
436 * if (pc->cap_usr_time && enabled != running) {
437 * cyc = rdtsc();
438 * time_offset = pc->time_offset;
439 * time_mult = pc->time_mult;
440 * time_shift = pc->time_shift;
441 * }
442 *
443 * index = pc->index;
444 * count = pc->offset;
445 * if (pc->cap_user_rdpmc && index) {
446 * width = pc->pmc_width;
447 * pmc = rdpmc(index - 1);
448 * }
449 *
450 * barrier();
451 * } while (pc->lock != seq);
452 *
453 * NOTE: for obvious reason this only works on self-monitoring
454 * processes.
455 */
456 __u32 lock; /* seqlock for synchronization */
457 __u32 index; /* hardware event identifier */
458 __s64 offset; /* add to hardware event value */
459 __u64 time_enabled; /* time event active */
460 __u64 time_running; /* time event on cpu */
461 union {
462 __u64 capabilities;
463 struct {
464 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */
465 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */
466
467 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */
468 cap_user_time : 1, /* The time_* fields are used */
469 cap_user_time_zero : 1, /* The time_zero field is used */
470 cap_____res : 59;
471 };
472 };
473
474 /*
475 * If cap_user_rdpmc this field provides the bit-width of the value
476 * read using the rdpmc() or equivalent instruction. This can be used
477 * to sign extend the result like:
478 *
479 * pmc <<= 64 - width;
480 * pmc >>= 64 - width; // signed shift right
481 * count += pmc;
482 */
483 __u16 pmc_width;
484
485 /*
486 * If cap_usr_time the below fields can be used to compute the time
487 * delta since time_enabled (in ns) using rdtsc or similar.
488 *
489 * u64 quot, rem;
490 * u64 delta;
491 *
492 * quot = (cyc >> time_shift);
493 * rem = cyc & (((u64)1 << time_shift) - 1);
494 * delta = time_offset + quot * time_mult +
495 * ((rem * time_mult) >> time_shift);
496 *
497 * Where time_offset,time_mult,time_shift and cyc are read in the
498 * seqcount loop described above. This delta can then be added to
499 * enabled and possible running (if index), improving the scaling:
500 *
501 * enabled += delta;
502 * if (index)
503 * running += delta;
504 *
505 * quot = count / running;
506 * rem = count % running;
507 * count = quot * enabled + (rem * enabled) / running;
508 */
509 __u16 time_shift;
510 __u32 time_mult;
511 __u64 time_offset;
512 /*
513 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
514 * from sample timestamps.
515 *
516 * time = timestamp - time_zero;
517 * quot = time / time_mult;
518 * rem = time % time_mult;
519 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
520 *
521 * And vice versa:
522 *
523 * quot = cyc >> time_shift;
524 * rem = cyc & (((u64)1 << time_shift) - 1);
525 * timestamp = time_zero + quot * time_mult +
526 * ((rem * time_mult) >> time_shift);
527 */
528 __u64 time_zero;
529 __u32 size; /* Header size up to __reserved[] fields. */
530
531 /*
532 * Hole for extension of the self monitor capabilities
533 */
534
535 __u8 __reserved[118*8+4]; /* align to 1k. */
536
537 /*
538 * Control data for the mmap() data buffer.
539 *
540 * User-space reading the @data_head value should issue an smp_rmb(),
541 * after reading this value.
542 *
543 * When the mapping is PROT_WRITE the @data_tail value should be
544 * written by userspace to reflect the last read data, after issueing
545 * an smp_mb() to separate the data read from the ->data_tail store.
546 * In this case the kernel will not over-write unread data.
547 *
548 * See perf_output_put_handle() for the data ordering.
549 *
550 * data_{offset,size} indicate the location and size of the perf record
551 * buffer within the mmapped area.
552 */
553 __u64 data_head; /* head in the data section */
554 __u64 data_tail; /* user-space written tail */
555 __u64 data_offset; /* where the buffer starts */
556 __u64 data_size; /* data buffer size */
557
558 /*
559 * AUX area is defined by aux_{offset,size} fields that should be set
560 * by the userspace, so that
561 *
562 * aux_offset >= data_offset + data_size
563 *
564 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size.
565 *
566 * Ring buffer pointers aux_{head,tail} have the same semantics as
567 * data_{head,tail} and same ordering rules apply.
568 */
569 __u64 aux_head;
570 __u64 aux_tail;
571 __u64 aux_offset;
572 __u64 aux_size;
573};
574
575#define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
576#define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
577#define PERF_RECORD_MISC_KERNEL (1 << 0)
578#define PERF_RECORD_MISC_USER (2 << 0)
579#define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
580#define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
581#define PERF_RECORD_MISC_GUEST_USER (5 << 0)
582
583/*
584 * Indicates that /proc/PID/maps parsing are truncated by time out.
585 */
586#define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12)
587/*
588 * PERF_RECORD_MISC_MMAP_DATA and PERF_RECORD_MISC_COMM_EXEC are used on
589 * different events so can reuse the same bit position.
590 * Ditto PERF_RECORD_MISC_SWITCH_OUT.
591 */
592#define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
593#define PERF_RECORD_MISC_COMM_EXEC (1 << 13)
594#define PERF_RECORD_MISC_SWITCH_OUT (1 << 13)
595/*
596 * Indicates that the content of PERF_SAMPLE_IP points to
597 * the actual instruction that triggered the event. See also
598 * perf_event_attr::precise_ip.
599 */
600#define PERF_RECORD_MISC_EXACT_IP (1 << 14)
601/*
602 * Reserve the last bit to indicate some extended misc field
603 */
604#define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
605
606struct perf_event_header {
607 __u32 type;
608 __u16 misc;
609 __u16 size;
610};
611
612enum perf_event_type {
613
614 /*
615 * If perf_event_attr.sample_id_all is set then all event types will
616 * have the sample_type selected fields related to where/when
617 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
618 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
619 * just after the perf_event_header and the fields already present for
620 * the existing fields, i.e. at the end of the payload. That way a newer
621 * perf.data file will be supported by older perf tools, with these new
622 * optional fields being ignored.
623 *
624 * struct sample_id {
625 * { u32 pid, tid; } && PERF_SAMPLE_TID
626 * { u64 time; } && PERF_SAMPLE_TIME
627 * { u64 id; } && PERF_SAMPLE_ID
628 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
629 * { u32 cpu, res; } && PERF_SAMPLE_CPU
630 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
631 * } && perf_event_attr::sample_id_all
632 *
633 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The
634 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
635 * relative to header.size.
636 */
637
638 /*
639 * The MMAP events record the PROT_EXEC mappings so that we can
640 * correlate userspace IPs to code. They have the following structure:
641 *
642 * struct {
643 * struct perf_event_header header;
644 *
645 * u32 pid, tid;
646 * u64 addr;
647 * u64 len;
648 * u64 pgoff;
649 * char filename[];
650 * struct sample_id sample_id;
651 * };
652 */
653 PERF_RECORD_MMAP = 1,
654
655 /*
656 * struct {
657 * struct perf_event_header header;
658 * u64 id;
659 * u64 lost;
660 * struct sample_id sample_id;
661 * };
662 */
663 PERF_RECORD_LOST = 2,
664
665 /*
666 * struct {
667 * struct perf_event_header header;
668 *
669 * u32 pid, tid;
670 * char comm[];
671 * struct sample_id sample_id;
672 * };
673 */
674 PERF_RECORD_COMM = 3,
675
676 /*
677 * struct {
678 * struct perf_event_header header;
679 * u32 pid, ppid;
680 * u32 tid, ptid;
681 * u64 time;
682 * struct sample_id sample_id;
683 * };
684 */
685 PERF_RECORD_EXIT = 4,
686
687 /*
688 * struct {
689 * struct perf_event_header header;
690 * u64 time;
691 * u64 id;
692 * u64 stream_id;
693 * struct sample_id sample_id;
694 * };
695 */
696 PERF_RECORD_THROTTLE = 5,
697 PERF_RECORD_UNTHROTTLE = 6,
698
699 /*
700 * struct {
701 * struct perf_event_header header;
702 * u32 pid, ppid;
703 * u32 tid, ptid;
704 * u64 time;
705 * struct sample_id sample_id;
706 * };
707 */
708 PERF_RECORD_FORK = 7,
709
710 /*
711 * struct {
712 * struct perf_event_header header;
713 * u32 pid, tid;
714 *
715 * struct read_format values;
716 * struct sample_id sample_id;
717 * };
718 */
719 PERF_RECORD_READ = 8,
720
721 /*
722 * struct {
723 * struct perf_event_header header;
724 *
725 * #
726 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
727 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position
728 * # is fixed relative to header.
729 * #
730 *
731 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
732 * { u64 ip; } && PERF_SAMPLE_IP
733 * { u32 pid, tid; } && PERF_SAMPLE_TID
734 * { u64 time; } && PERF_SAMPLE_TIME
735 * { u64 addr; } && PERF_SAMPLE_ADDR
736 * { u64 id; } && PERF_SAMPLE_ID
737 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
738 * { u32 cpu, res; } && PERF_SAMPLE_CPU
739 * { u64 period; } && PERF_SAMPLE_PERIOD
740 *
741 * { struct read_format values; } && PERF_SAMPLE_READ
742 *
743 * { u64 nr,
744 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN
745 *
746 * #
747 * # The RAW record below is opaque data wrt the ABI
748 * #
749 * # That is, the ABI doesn't make any promises wrt to
750 * # the stability of its content, it may vary depending
751 * # on event, hardware, kernel version and phase of
752 * # the moon.
753 * #
754 * # In other words, PERF_SAMPLE_RAW contents are not an ABI.
755 * #
756 *
757 * { u32 size;
758 * char data[size];}&& PERF_SAMPLE_RAW
759 *
760 * { u64 nr;
761 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK
762 *
763 * { u64 abi; # enum perf_sample_regs_abi
764 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
765 *
766 * { u64 size;
767 * char data[size];
768 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
769 *
770 * { u64 weight; } && PERF_SAMPLE_WEIGHT
771 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC
772 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION
773 * { u64 abi; # enum perf_sample_regs_abi
774 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
775 * };
776 */
777 PERF_RECORD_SAMPLE = 9,
778
779 /*
780 * The MMAP2 records are an augmented version of MMAP, they add
781 * maj, min, ino numbers to be used to uniquely identify each mapping
782 *
783 * struct {
784 * struct perf_event_header header;
785 *
786 * u32 pid, tid;
787 * u64 addr;
788 * u64 len;
789 * u64 pgoff;
790 * u32 maj;
791 * u32 min;
792 * u64 ino;
793 * u64 ino_generation;
794 * u32 prot, flags;
795 * char filename[];
796 * struct sample_id sample_id;
797 * };
798 */
799 PERF_RECORD_MMAP2 = 10,
800
801 /*
802 * Records that new data landed in the AUX buffer part.
803 *
804 * struct {
805 * struct perf_event_header header;
806 *
807 * u64 aux_offset;
808 * u64 aux_size;
809 * u64 flags;
810 * struct sample_id sample_id;
811 * };
812 */
813 PERF_RECORD_AUX = 11,
814
815 /*
816 * Indicates that instruction trace has started
817 *
818 * struct {
819 * struct perf_event_header header;
820 * u32 pid;
821 * u32 tid;
822 * };
823 */
824 PERF_RECORD_ITRACE_START = 12,
825
826 /*
827 * Records the dropped/lost sample number.
828 *
829 * struct {
830 * struct perf_event_header header;
831 *
832 * u64 lost;
833 * struct sample_id sample_id;
834 * };
835 */
836 PERF_RECORD_LOST_SAMPLES = 13,
837
838 /*
839 * Records a context switch in or out (flagged by
840 * PERF_RECORD_MISC_SWITCH_OUT). See also
841 * PERF_RECORD_SWITCH_CPU_WIDE.
842 *
843 * struct {
844 * struct perf_event_header header;
845 * struct sample_id sample_id;
846 * };
847 */
848 PERF_RECORD_SWITCH = 14,
849
850 /*
851 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and
852 * next_prev_tid that are the next (switching out) or previous
853 * (switching in) pid/tid.
854 *
855 * struct {
856 * struct perf_event_header header;
857 * u32 next_prev_pid;
858 * u32 next_prev_tid;
859 * struct sample_id sample_id;
860 * };
861 */
862 PERF_RECORD_SWITCH_CPU_WIDE = 15,
863
864 PERF_RECORD_MAX, /* non-ABI */
865};
866
867#define PERF_MAX_STACK_DEPTH 127
868#define PERF_MAX_CONTEXTS_PER_STACK 8
869
870enum perf_callchain_context {
871 PERF_CONTEXT_HV = (__u64)-32,
872 PERF_CONTEXT_KERNEL = (__u64)-128,
873 PERF_CONTEXT_USER = (__u64)-512,
874
875 PERF_CONTEXT_GUEST = (__u64)-2048,
876 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176,
877 PERF_CONTEXT_GUEST_USER = (__u64)-2560,
878
879 PERF_CONTEXT_MAX = (__u64)-4095,
880};
881
882/**
883 * PERF_RECORD_AUX::flags bits
884 */
885#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */
886#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */
887
888#define PERF_FLAG_FD_NO_GROUP (1UL << 0)
889#define PERF_FLAG_FD_OUTPUT (1UL << 1)
890#define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */
891#define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
892
893union perf_mem_data_src {
894 __u64 val;
895 struct {
896 __u64 mem_op:5, /* type of opcode */
897 mem_lvl:14, /* memory hierarchy level */
898 mem_snoop:5, /* snoop mode */
899 mem_lock:2, /* lock instr */
900 mem_dtlb:7, /* tlb access */
901 mem_rsvd:31;
902 };
903};
904
905/* type of opcode (load/store/prefetch,code) */
906#define PERF_MEM_OP_NA 0x01 /* not available */
907#define PERF_MEM_OP_LOAD 0x02 /* load instruction */
908#define PERF_MEM_OP_STORE 0x04 /* store instruction */
909#define PERF_MEM_OP_PFETCH 0x08 /* prefetch */
910#define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
911#define PERF_MEM_OP_SHIFT 0
912
913/* memory hierarchy (memory level, hit or miss) */
914#define PERF_MEM_LVL_NA 0x01 /* not available */
915#define PERF_MEM_LVL_HIT 0x02 /* hit level */
916#define PERF_MEM_LVL_MISS 0x04 /* miss level */
917#define PERF_MEM_LVL_L1 0x08 /* L1 */
918#define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */
919#define PERF_MEM_LVL_L2 0x20 /* L2 */
920#define PERF_MEM_LVL_L3 0x40 /* L3 */
921#define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */
922#define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */
923#define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */
924#define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */
925#define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */
926#define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
927#define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
928#define PERF_MEM_LVL_SHIFT 5
929
930/* snoop mode */
931#define PERF_MEM_SNOOP_NA 0x01 /* not available */
932#define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */
933#define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */
934#define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
935#define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */
936#define PERF_MEM_SNOOP_SHIFT 19
937
938/* locked instruction */
939#define PERF_MEM_LOCK_NA 0x01 /* not available */
940#define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */
941#define PERF_MEM_LOCK_SHIFT 24
942
943/* TLB access */
944#define PERF_MEM_TLB_NA 0x01 /* not available */
945#define PERF_MEM_TLB_HIT 0x02 /* hit level */
946#define PERF_MEM_TLB_MISS 0x04 /* miss level */
947#define PERF_MEM_TLB_L1 0x08 /* L1 */
948#define PERF_MEM_TLB_L2 0x10 /* L2 */
949#define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/
950#define PERF_MEM_TLB_OS 0x40 /* OS fault handler */
951#define PERF_MEM_TLB_SHIFT 26
952
953#define PERF_MEM_S(a, s) \
954 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
955
956/*
957 * single taken branch record layout:
958 *
959 * from: source instruction (may not always be a branch insn)
960 * to: branch target
961 * mispred: branch target was mispredicted
962 * predicted: branch target was predicted
963 *
964 * support for mispred, predicted is optional. In case it
965 * is not supported mispred = predicted = 0.
966 *
967 * in_tx: running in a hardware transaction
968 * abort: aborting a hardware transaction
969 * cycles: cycles from last branch (or 0 if not supported)
970 */
971struct perf_branch_entry {
972 __u64 from;
973 __u64 to;
974 __u64 mispred:1, /* target mispredicted */
975 predicted:1,/* target predicted */
976 in_tx:1, /* in transaction */
977 abort:1, /* transaction abort */
978 cycles:16, /* cycle count to last branch */
979 reserved:44;
980};
981
982#endif /* _UAPI_LINUX_PERF_EVENT_H */
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