update

git-svn-id: http://ltt.polymtl.ca/svn@2875 04897980-b3bd-0310-b5e0-8ef037075253

diff --git a/markers-test/Makefile b/markers-test/Makefile
index d07a82928c45ce5427d764952ae3baca0c715abe..4499bb27f9589dbd056c6e431c9efdda1452ba45 100644 (file)
--- a/markers-test/Makefile
+++ b/markers-test/Makefile
@@ -4,7 +4,6 @@ ifneq ($(KERNELRELEASE),)
        obj-m += test-mark-speed-edit.o
        obj-m += test-mark-speed-opt.o
        obj-m += test-mark-speed-local.o
-       obj-m += cachectl.o
 else
        KERNELDIR ?= /lib/modules/$(shell uname -r)/build
        PWD := $(shell pwd)

diff --git a/markers-test/test-mark-speed-edit.c b/markers-test/test-mark-speed-edit.c
index 5e104563a1f4bd76ff4282e6de59d3c79b3554ac..ebae25d26036f61ae95f0e5898a05daf7f0deeaa 100644 (file)
--- a/markers-test/test-mark-speed-edit.c
+++ b/markers-test/test-mark-speed-edit.c
@@ -10,6 +10,27 @@
 #include <asm/ptrace.h>
 #include <asm/system.h>
 
+static void pmc_flush_cache(void)
+  {
+    /* write back and invalidate cache (a serializing instruction) */
+
+    __asm__ __volatile__ ( "wbinvd" : : : "memory" );
+
+    /* The wbinvd instruction does not wait for the external caches
+     * to be flushed, but only requests that it be done.  The loop
+     * is to be sure that enough time has elapsed, but the compiler
+     * might simplify or even remove it.  The loop bound is for a
+     * 512 KB L2 cache.  On a Pentium Pro/II/III, the loop uses
+     * 2 cycles per iteration.
+     *
+     * Does wbinvd also cause the TLB to be flushed?
+     * A comment in mtrr.c suggests that it does.
+     */
+    { register int i; for (i = 0; i < 512*1024; i++) { } }
+  }
+
+
+
 static void noinline test2(const struct marker *mdata,
         void *call_private, ...)
 {
@@ -69,7 +90,7 @@ char temp5[8192];
 static inline void test(unsigned long arg, unsigned long arg2)
 {
 #ifdef CACHEFLUSH
-       wbinvd();
+       pmc_flush_cache();
 #endif
        temp[2] = (temp[0] + 60) << 10;
        temp[3] = (temp[2] + 60) << 10;
@@ -91,7 +112,7 @@ static int my_open(struct inode *inode, struct file *file)
 
        local_irq_save(flags);
 #ifdef CACHEFLUSH
-       wbinvd();       /* initial write back, without cycle count */
+       pmc_flush_cache();      /* initial write back, without cycle count */
        msleep(20);     /* wait for L2 flush */
 #endif
        rdtsc_barrier();

diff --git a/markers-test/test-mark-speed-empty.c b/markers-test/test-mark-speed-empty.c
index ceaac9da04616a66eca206e0da81f35cdc9d4c37..a247cacb497c1be7e8368b239f0cf6f6e4cf959a 100644 (file)
--- a/markers-test/test-mark-speed-empty.c
+++ b/markers-test/test-mark-speed-empty.c
@@ -10,6 +10,26 @@
 #include <asm/ptrace.h>
 #include <asm/system.h>
 
+static void pmc_flush_cache(void)
+  {
+    /* write back and invalidate cache (a serializing instruction) */
+
+    __asm__ __volatile__ ( "wbinvd" : : : "memory" );
+
+    /* The wbinvd instruction does not wait for the external caches
+     * to be flushed, but only requests that it be done.  The loop
+     * is to be sure that enough time has elapsed, but the compiler
+     * might simplify or even remove it.  The loop bound is for a
+     * 512 KB L2 cache.  On a Pentium Pro/II/III, the loop uses
+     * 2 cycles per iteration.
+     *
+     * Does wbinvd also cause the TLB to be flushed?
+     * A comment in mtrr.c suggests that it does.
+     */
+    { register int i; for (i = 0; i < 512*1024; i++) { } }
+  }
+
+
 static void noinline test2(const struct marker *mdata,
         void *call_private, ...)
 {
@@ -59,7 +79,7 @@ char temp5[8192];
 static inline void test(unsigned long arg, unsigned long arg2)
 {
 #ifdef CACHEFLUSH
-       wbinvd();
+       pmc_flush_cache();
 #endif
        temp[2] = (temp[0] + 60) << 10;
        temp[3] = (temp[2] + 60) << 10;
@@ -80,7 +100,7 @@ static int my_open(struct inode *inode, struct file *file)
 
        local_irq_save(flags);
 #ifdef CACHEFLUSH
-       wbinvd();       /* initial write back, without cycle count */
+       pmc_flush_cache();      /* initial write back, without cycle count */
        msleep(20);     /* wait for L2 flush */
 #endif
        rdtsc_barrier();

diff --git a/markers-test/test-mark-speed-local.c b/markers-test/test-mark-speed-local.c
index 5bcbccb7b2ee1ea9c892142f75e5001628eec9da..552afcea23f84c2e074db9c643b7faa27978392c 100644 (file)
--- a/markers-test/test-mark-speed-local.c
+++ b/markers-test/test-mark-speed-local.c
@@ -10,6 +10,26 @@
 #include <asm/ptrace.h>
 #include <asm/system.h>
 
+static void pmc_flush_cache(void)
+  {
+    /* write back and invalidate cache (a serializing instruction) */
+
+    __asm__ __volatile__ ( "wbinvd" : : : "memory" );
+
+    /* The wbinvd instruction does not wait for the external caches
+     * to be flushed, but only requests that it be done.  The loop
+     * is to be sure that enough time has elapsed, but the compiler
+     * might simplify or even remove it.  The loop bound is for a
+     * 512 KB L2 cache.  On a Pentium Pro/II/III, the loop uses
+     * 2 cycles per iteration.
+     *
+     * Does wbinvd also cause the TLB to be flushed?
+     * A comment in mtrr.c suggests that it does.
+     */
+    { register int i; for (i = 0; i < 512*1024; i++) { } }
+  }
+
+
 static void noinline test2(const struct marker *mdata,
         void *call_private, ...)
 {
@@ -68,7 +88,7 @@ char temp5[8192];
 static inline void test(unsigned long arg, unsigned long arg2)
 {
 #ifdef CACHEFLUSH
-       wbinvd();
+       pmc_flush_cache();
 #endif
        temp[2] = (temp[0] + 60) << 10;
        temp[3] = (temp[2] + 60) << 10;
@@ -90,7 +110,7 @@ static int my_open(struct inode *inode, struct file *file)
 
        local_irq_save(flags);
 #ifdef CACHEFLUSH
-       wbinvd();       /* initial write back, without cycle count */
+       pmc_flush_cache();      /* initial write back, without cycle count */
        msleep(20);     /* wait for L2 flush */
 #endif
        rdtsc_barrier();

diff --git a/markers-test/test-mark-speed-opt.c b/markers-test/test-mark-speed-opt.c
index aa7c2ca6f667d06d68e64f83d5fedbc22e270466..231285d14cc17cbb306a1e8b7d478dbe9c149347 100644 (file)
--- a/markers-test/test-mark-speed-opt.c
+++ b/markers-test/test-mark-speed-opt.c
@@ -10,6 +10,26 @@
 #include <asm/ptrace.h>
 #include <asm/system.h>
 
+static void pmc_flush_cache(void)
+  {
+    /* write back and invalidate cache (a serializing instruction) */
+
+    __asm__ __volatile__ ( "wbinvd" : : : "memory" );
+
+    /* The wbinvd instruction does not wait for the external caches
+     * to be flushed, but only requests that it be done.  The loop
+     * is to be sure that enough time has elapsed, but the compiler
+     * might simplify or even remove it.  The loop bound is for a
+     * 512 KB L2 cache.  On a Pentium Pro/II/III, the loop uses
+     * 2 cycles per iteration.
+     *
+     * Does wbinvd also cause the TLB to be flushed?
+     * A comment in mtrr.c suggests that it does.
+     */
+    { register int i; for (i = 0; i < 512*1024; i++) { } }
+  }
+
+
 static void noinline test2(const struct marker *mdata,
         void *call_private, ...)
 {
@@ -58,7 +78,7 @@ char temp5[8192];
 static inline void test(unsigned long arg, unsigned long arg2)
 {
 #ifdef CACHEFLUSH
-       wbinvd();
+       pmc_flush_cache();
 #endif
        temp[2] = (temp[0] + 60) << 10;
        temp[3] = (temp[2] + 60) << 10;
@@ -79,7 +99,7 @@ static int my_open(struct inode *inode, struct file *file)
 
        local_irq_save(flags);
 #ifdef CACHEFLUSH
-       wbinvd();       /* initial write back, without cycle count */
+       pmc_flush_cache();      /* initial write back, without cycle count */
        msleep(20);     /* wait for L2 flush */
 #endif
        rdtsc_barrier();

diff --git a/markers-test/test-mark-speed.c b/markers-test/test-mark-speed.c
index 25f45a1a8df08a35586fbbc8614cf87e2bec2a28..bd798b8e3de39eda060cec129b48f0ff69aaa9aa 100644 (file)
--- a/markers-test/test-mark-speed.c
+++ b/markers-test/test-mark-speed.c
@@ -10,6 +10,25 @@
 #include <asm/ptrace.h>
 #include <asm/system.h>
 
+static void pmc_flush_cache(void)
+  {
+    /* write back and invalidate cache (a serializing instruction) */
+
+    __asm__ __volatile__ ( "wbinvd" : : : "memory" );
+
+    /* The wbinvd instruction does not wait for the external caches
+     * to be flushed, but only requests that it be done.  The loop
+     * is to be sure that enough time has elapsed, but the compiler
+     * might simplify or even remove it.  The loop bound is for a
+     * 512 KB L2 cache.  On a Pentium Pro/II/III, the loop uses
+     * 2 cycles per iteration.
+     *
+     * Does wbinvd also cause the TLB to be flushed?
+     * A comment in mtrr.c suggests that it does.
+     */
+    { register int i; for (i = 0; i < 512*1024; i++) { } }
+  }
+
 static void noinline test2(const struct marker *mdata,
         void *call_private, ...)
 {
@@ -59,7 +78,7 @@ char temp5[8192];
 static inline void test(unsigned long arg, unsigned long arg2)
 {
 #ifdef CACHEFLUSH
-       wbinvd();
+       pmc_flush_cache();
 #endif
        temp[2] = (temp[0] + 60) << 10;
        temp[3] = (temp[2] + 60) << 10;
@@ -80,7 +99,7 @@ static int my_open(struct inode *inode, struct file *file)
 
        local_irq_save(flags);
 #ifdef CACHEFLUSH
-       wbinvd();       /* initial write back, without cycle count */
+       pmc_flush_cache();      /* initial write back, without cycle count */
        msleep(20);     /* wait for L2 flush */
 #endif
        rdtsc_barrier();