synthetic tsc update

git-svn-id: http://ltt.polymtl.ca/svn@1568 04897980-b3bd-0310-b5e0-8ef037075253

diff --git a/ltt/branches/poly/doc/developer/lttng-synthetic-tsc-msb.txt b/ltt/branches/poly/doc/developer/lttng-synthetic-tsc-msb.txt
index f59d7c737fe19bf402a618877b93668d03c6ead8..ffac4289ca8c12cfe171c9a3a46ca078c158a99c 100644 (file)
--- a/ltt/branches/poly/doc/developer/lttng-synthetic-tsc-msb.txt
+++ b/ltt/branches/poly/doc/developer/lttng-synthetic-tsc-msb.txt
@@ -48,4 +48,5 @@ An array of two 64 bits elements. Elements are updated in two memory writes, but
 the element switch (current element) is made atomically. As there is only one
 writer, this has no locking problem.
 
-
+We make sure the synthetic tcs reader does not sleep by disabling preemption. We
+do the same for the writer.