update

git-svn-id: http://ltt.polymtl.ca/svn@2878 04897980-b3bd-0310-b5e0-8ef037075253

diff --git a/markers-test/test-mark-speed-edit.c b/markers-test/test-mark-speed-edit.c
index 2aeab6e2a9347ac80cc8f59dd28788ab9802dde9..3c8964f17fd1b4746fdb86bc5bbf16133c48ac35 100644 (file)
--- a/markers-test/test-mark-speed-edit.c
+++ b/markers-test/test-mark-speed-edit.c
@@ -12,6 +12,7 @@
 
 static void pmc_flush_cache(void)
   {
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,7 +27,10 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
+    
+     for (i = 0; i < 512*1024; i++) {
+       cpu_relax();
+     }
   }
 
 
@@ -85,7 +89,7 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-       register int temp[5];
+       volatile int temp[5];
 #ifdef CACHEFLUSH
        pmc_flush_cache();
 #endif

diff --git a/markers-test/test-mark-speed-empty.c b/markers-test/test-mark-speed-empty.c
index caaf907e889405f167688e709150deca8d6a7bdb..edae0550d0d5751d7fce45ec10952ad1befa19fd 100644 (file)
--- a/markers-test/test-mark-speed-empty.c
+++ b/markers-test/test-mark-speed-empty.c
@@ -12,6 +12,7 @@
 
 static void pmc_flush_cache(void)
   {
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,7 +27,9 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
+    for (i = 0; i < 512*1024; i++) {
+      cpu_relax();
+    }
   }
 
 
@@ -74,7 +77,7 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-       register int temp[5];
+       volatile int temp[5];
 #ifdef CACHEFLUSH
        pmc_flush_cache();
 #endif

diff --git a/markers-test/test-mark-speed-local.c b/markers-test/test-mark-speed-local.c
index e0bb5fd47163bea0e2f42eef547bdbfe3501133f..63d8f9dcfc04f6c04989755572b1aaf19a560262 100644 (file)
--- a/markers-test/test-mark-speed-local.c
+++ b/markers-test/test-mark-speed-local.c
@@ -12,6 +12,7 @@
 
 static void pmc_flush_cache(void)
   {
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,7 +27,9 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
+    for (i = 0; i < 512*1024; i++) {
+      cpu_relax();
+    }
   }
 
 
@@ -83,7 +86,7 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-       register int temp[5];
+       volatile int temp[5];
 #ifdef CACHEFLUSH
        pmc_flush_cache();
 #endif

diff --git a/markers-test/test-mark-speed-opt.c b/markers-test/test-mark-speed-opt.c
index d1f716b96f8e50d333386dbeb433c98aac31de09..755a41a94812c049c85270943d1d41d3f99b84ea 100644 (file)
--- a/markers-test/test-mark-speed-opt.c
+++ b/markers-test/test-mark-speed-opt.c
@@ -12,6 +12,7 @@
 
 static void pmc_flush_cache(void)
   {
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,7 +27,9 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
+    for (i = 0; i < 512*1024; i++) {
+      cpu_relax();
+    }
   }
 
 
@@ -73,7 +76,7 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-       register int temp[5];
+       volatile int temp[5];
 #ifdef CACHEFLUSH
        pmc_flush_cache();
 #endif

diff --git a/markers-test/test-mark-speed.c b/markers-test/test-mark-speed.c
index 6658e645795418933e128db036f3fdfc9f0d668d..c000df081e4d26c3412ebe2d8eddbf4fc1fe981e 100644 (file)
--- a/markers-test/test-mark-speed.c
+++ b/markers-test/test-mark-speed.c
@@ -11,7 +11,8 @@
 #include <asm/system.h>
 
 static void pmc_flush_cache(void)
-  {
+{
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,8 +27,10 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
-  }
+    for (i = 0; i < 512*1024; i++) {
+       cpu_relax();
+    }
+}
 
 static void noinline test2(const struct marker *mdata,
         void *call_private, ...)
@@ -73,7 +76,7 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-       register int temp[5];
+       volatile int temp[5];
 #ifdef CACHEFLUSH
        pmc_flush_cache();
 #endif